Niagara-2 will double the single-thread performance of the first-generation device, in part by greater sharing of hardware and other tricks the company will not yet disclose. It will still have a maximum of eight cores, but those cores will run eight rather than four threads each, without creating significant resource contention.
"We are seeing linear scaling [on the 64-thread version]," Splain said.
The processor will also be Sun's first to go entirely serial. It will integrate an 8x PCI Express interface to eliminate the separate J-Bus chip. It will also integrate a new ground-up processor interconnect to open the door to systems with two Niagara chips.
Putting Express directly on a server processor is new, but "this will be a trend," Splain said. "Competitors are doing it, and you will see more of it."
Sun has access to 8x Express through LSI Logic, which supplied the intellectual property for the current J-Bus bridge chip. It also has an internally developed Express block.
The resulting Niagara-2 board may have as few as half the 22 layers in the current pc board. The board also will be significantly smaller and less costly because not only the Express interconnect but a multiport Gbit Ethernet switch will be integrated in Niagara-2.
Also, Niagara-2 will include hardware support for bulk encryption algorithms including AES, 3DES and elliptical curve cryptography. By putting most of the I/O board components into the processor, Sun makes room for the two-chip system.
DIMMs get nod
The Niagara-2 server will also use fully buffered DIMMs. These emerging memories are initially expected to add power consumption and latency to server designs, but "this technology is the best solution to the memory expansion problems all server makers have," Splain said.
Sun acquired the Niagara design in July 2002 from startup Afara Websystems Inc., led by former Sparc designer Les Kohn. Most of Afara's 60 processor designers stayed on at Sun. Sun veteran Rick Hetherington became chief architect of Niagara.
The Afara design, similar to the Niagara-2 plan, included networking, encryption and a proprietary interconnect to link multiple CPU cards in a chassis. Sun tore out much of the integration for the first-generation part in an effort to reduce die size, technology risks and time-to-market.
Encryption in the Afara device required a 3- to 4-mm2 block per core. "At 90 nm, that took a fairly large part of the die area," Splain said. As for Ethernet, "the value proposition was the threads, not networking," he added. The first-generation Niagara still has hardware acceleration for modular arithmetic to speed operations.
Sun also took off the PCI-X interface on the Afara device, choosing to use its J-Bus instead as a transition to Express. The company also removed the proprietary clustering interconnect, something it's keeping in a back pocket, potentially for Niagara-2. "We left the hardest parts alone: the core, threads, cache coherency, crossbar switch and load/store mechanisms," Splain said.
Afar had incomplete RTL code and a "fairly immature" design when it was acquired. "They were targeting a different fab as well, not TI," said Hetherington.
