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21 August 2008



Optical chip-to-chip connections advance

By Elisabeth Marley Koontz
Courtesy of EE Times
Nov 10, 2003
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Optical chip-to-chip connec-tions are an active area of investigation within both the industrial and academic sectors of the optical-communications market. The attractiveness of the concept for semiconductor suppliers and their OEM customers is the possibility of realizing optical links across high-speed electronic backplanes and motherboards.

The desire for an optical chip-to-chip solution is driven by the I/O needs of future communication systems and the increasingly complex ASICs, microprocessors and digital signal processors that support the system architectures. An optical chip-to-chip communication scheme is an attractive solution to the power, density and signal isolation issues in high-throughput, compact systems.

When considering such schemes, it is important to understand that electrons will continue to power the data-processing engine while photons will be the data path conduit. This means the optical solution must be compatible with the electronics components and vice versa. Further, the optical solution will compete to replace a low-cost, optimized solution with strong support across standards bodies and manufacturers, so it must offer compelling benefits to succeed.

Electronic I/O management schemes are typically serializer/deserializer devices and are monolithically integrated in the ICs. Using serdes to multiplex the data processed by each IC reduces the resulting number of I/O ports. The appeal of an optical solution lies in its ability to further maximize the data rate and distance of data transmission between ICs. An optical solution can also further reduce the number of connections using wavelength-division multiplexing (WDM) or optical time-division multiplexing (TDM).

The design community is approaching consensus on a hybrid solution in which the optical components are manufactured independently and attached to the electronic ones via flip-chip, multichip-module or system-on-package schemes. Most of the solutions investigated to date have focused on a vertical approach, typically utilizing vertical-cavity surface-emitting lasers or vertical modulators and detectors. A single additional chip containing all the optical functionality would likewise be an attractive solution. Another possibility is to embed thinned optical devices in polymer waveguides and connect the electronics to the substrate or package containing the polymer waveguides.

Thermal issues

A number of critical issues remain, including multimode vs. single mode, on-chip vs. off-chip optical source, WDM vs. TDM or no multiplexing, and polymer waveguides vs. free-space connections. For data rates of 10 Gbits/second and above (the speed at which an optical chip-to-chip solution begins to be attractive), multimode solutions are challenging because of modal dispersion.

On-chip sources will be difficult to manage, especially thermally, for high-I/O-port ICs such as microprocessors; off-chip sources have the advantage of being independently controlled and monitored, yet coupling the off-chip light source to the optical chip or modulator adds complexity. WDM solutions require a minimal number of input/output paths. Manipulation of WDM is typically space-consuming, however, and requires either multiple-wavelength, precise lasers or a single, costly, mode-locked laser.

The polymer quality or free-space architecture is particularly important when considering reasonable distances between the communicating chips-and more significantly so for single-mode than multimode solutions. Sophisticated packaging schemes will also be required to address thermal management of dissimilar materials and temperature-sensitive devices, coupling and the need for electronic packaging pick-and-place alignment tolerance.

At the moment, both optical and electronic suppliers are evaluating these paths. The ultimate implementation will lie in a joint solution that fits well into the economic model of all parties.

Elisabeth Marley Koontz is photonics strategy manager for silicon technology development at Texas Instruments Inc.




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