RapidIO has traditionally been used to handle the movement of control plane traffic in equipment designs. But with the serial version of the RapidIO spec available, and with cost-cutting still important, some major equipment vendors have pushed to add flow control mechanisms that will let RapidIO handle data plane traffic as well, said Sam Fuller, president of the RapidIO Trade Association, an industry group that develops and promotes the spec.

After a year of work, the association is adding end-to-end flow control mechanisms to its logical layer, allowing those mechanisms to work with both the serial and parallel versions of RapidIO, said Greg Shippen, chairman of the RapidIO Technical Working Group. "We didn't have to crack the foundation, insert the flow control mechanisms and patch it up again," Shippen said. "We built the mechanisms right on top of the existing protocols."

"If you're going to work in the data plane," said senior analyst Jag Bolaria at The Linley Group (Mountain View, Calif.), "flow control is just one of those things you've got to have."

In essence, the spec's added flow control mechanisms are designed to tackle such situations as congestion caused by head-of-line blocking. In that situation, output FIFOs in a network architecture begin to back up when rising network loads exceed the capacity of a link. Shippen said this type of blocking can cause backups in traffic streams accessing the congested link as well as in streams that enter the same switch but don't use the congested link. To address the problem, the trade association has added a congestion control packet (CCP) at the logical layer. When congestion on a link grows, the CCP sends a high-priority XOFF message through the net, telling systems to stop sending traffic to the congested link for a while. Once the congestion is cleared, Shippen said, an XON informs nodes that traffic can resume.

If an XOFF message is lost during transmission, the flow control mechanism can resend it. If an XON message is not received at the destination, the destination node will wait a period of time and then automatically begin sending traffic to the congested link, Shippen said.

The current RapidIO spec defines three flow control mechanisms, whereby flows in ascending priority receive increasingly better service (lower latency). The flows are intended to allow multiple data streams between endpoint devices that have no required ordering between them, Shippen said. "Priority" bits in the physical layer manage and prioritize the flows. They also enforce ordering and provide deadlock avoidance. "The degree to which individual flows receive better service is implementation-dependent," Shippen said. "However, the specification requires all switches to provide at least some minimum level of improved service for higher-priority flows because the priority bits are used for two purposes at once: to enforce ordering and provide deadlock avoidance at the physical layer, and to map logical-flow priority at the logical layer."

While only three flows are defined in the initial spec, there's a move within the trade association to add more precise flow control mechanisms.

With flow control procedures in place and more coming, the RapidIO Trade Association claims a lead over the PCI Express-based Advanced Switching spec, which is backed by Intel Corp. and dozens of supporting companies.

Robert Keenan is editor in chief of CommsDesign.com, an EE Times Network Web site.