Portable wireless devices are becoming smaller, lighter, and more powerful with each new generation of cell phone technology. In the eyes of users, this trend is a wonderful addition. For designers, on the other hand, this move creates new strains and challenges on their already tight power budgets.
The output power amplification (PA) stage consumes a big part of the battery capacity in a portable device. Therefore, by reducing consumption in the PA stage, designers can achieve a profound impact on overall device battery life.
While there are well-understood methods for improving PA efficiency through bias point setting, these methods are not compatible with complex, very dynamic modulations used in current digital wireless devices. The dynamic characteristics of these digital modulation techniques (QPSK, HPSK, DQPSK) require the PA stage to be very linear as to not degrade the quality of the signal and prevent the signal from "smearing" into adjacent channels, interfering with other wireless devices.
Fortunately, there are methods available to combine baseband signal processing with basic analog/RF signal processing to "linearize" the PA, while still maintaining relatively high efficiency. Polar modulation is one of the more common techniques used by designers today.
In this article, we'll dive into details on how the polar modulation architecture works. Simulation techniques will also be highlighted to show the overall performance gains provided by polar modulation.
Polar Mod Basics
There are many traditional methods for improving PA efficiency. A simple method is to limit the conduction angle of the PA so that it only amplifies for a limited portion of the carrier cycle. By limiting the duty cycle of conduction, reasonable output power can be achieved with very good efficiency. However, this type of amplification will distort the carrier waveform and, for many modulation types, will significantly degrade the quality of the modulation.
One form of modulation that is not impaired by this non-linear amplification is phase modulation (PM). Given that PM is not affected by highly non-linear amplification, a PM modulated signal can be faithfully reproduced with good efficiency.
The challenge designers face, however, is isolating the phase modulation component. In a typical modulation format, both PM and amplitude modulation (AM) are carried in the same waveform, making it difficult to use non-linear amplification techniques.
Enter polar modulation. Through polar modulation, designers can separate the AM component out of the waveform, amplifying only the remaining phase modulated signal. The AM component is then re-inserted after the amplification stage to restore the modulation back to its original form.
To facilitate reconstruction of the AM component, the input bias on the PA can be optimized such that the PM signal is hard limited, basically pushing the PA into a Class E state (switched mode). With the PM component hard limited, the fundamental output power of the PA can be made proportional to the square of the drain bias voltage.
The drain bias voltage can then be modulated with the AM component to effectively recombine the AM information with the PM information. When this is done properly, the intended modulation can be faithfully reconstructed, with low distortion, while maintaining very high PA power efficiency.
Figure 1 gives a block diagram of a basic system using the polar modulation technique described above.
Figure 1: Block diagram of a simple feed forward polar modulator.
The polar modulation technique shown in Figure 1 is a type of feed-forward linearization. To make the system function properly, the gain and delay characteristics of the PA must be understood so the magnitude and phase paths can be properly synchronized for minimum modulation distortion at the output. Digital signal processing (DSP) technology allows the PA characteristics to be stored in memory to account for variations with temperature and voltage (bias).
A slightly more advanced topology employs a feedback loop with the PA output magnitude. This basic control loop accounts for variations in PA gain due to temperature and aging as well as any non-linearities in the magnitude feed forward path. Sigma-delta modulation is used in the feedback path to provide a stable control voltage to the PA drain bias for magnitude reconstruction. Figure 2 shows a block diagram of a feedback system.
Figure 2: Block diagram of a feedback polar modulator.
Simulating a Basic Polar Modulation System
While many mathematical simulation frameworks can be used to model PA linearization systems such as polar modulation, a framework was chosen that allows accurate modeling of the complex modulating waveform as a baseband signal, along with accurate, non-linear modeling of the RF processing. It is useful to use behavioral models at various levels of modeling abstraction to facilitate efficient and accurate exploration of a prototype system. For the example in this article, the Advanced Design System (ADS) and its system simulator, Ptolemy, are used to demonstrate the polar linearization system presented.
Figure 3 shows a simple, first-pass simulation schematic of a polar modulation system, using very high-level behavioral models. The system employs EDGE modulation according to the ETSI GSM specification.
Figure 3: The simulation schematic of a basic, feed-forward polar modulator.
Note in this schematic the use of a very abstract PA behavioral model that allows parametric non-linear modeling of PA characteristics, in other words, TOI, 1-dB compression or AM-to-AM/AM-to-PM. By allowing this high level behavioral model to be non-linear, we can drive the input PM signal sufficiently hard to emulate the Class E nature of the actual amplifier. While not shown Figure 3, the amplifier behavioral model can be replaced with an actual circuit- or IC-level amplifier to model the system with more fidelity.
To analyze the performance of this system, the simulation was linked to vector signal analyzer (VSA) software for demodulation and analysis (Figure 4). This link allows the designer to maintain measurement consistency from high level design and simulation through actual prototype measurement in the lab.
Figure 4: The simulation results for a basic polar modulation system.
Figure 4 shows the simulation results of this simple, conceptual polar modulation system. Note that EVM for the reconstructed signal is below 1 percent, which will become our reference for subsequent simulations. As we add more detail to the signal processing and to the fidelity of the PA model, we expect this to degrade, but to still meet the ETSI requirements by a considerable margin.
Circuit-Level PA Design
A simple PA design was constructed to use as a test case to prove the above linearization method. The PA circuit, shown in Figure 5, was constructed using a generic GaAs FET model and was matched using standard lumped element components.
Figure 5: The circuit schematic for the evaluation power amplifier.
The gate bias on the PA shown in Figure 5 was established to allow the input RF waveform to drive the amplifier into hard compression over the desired output drain bias voltage range. Figure 5 also shows the schematic of this simple PA circuit with a very simple output match. Using the frequency domain non-linear harmonic balance simulator, this amplifier was simulated to determine the appropriate drive level required to place the amplifier into a Class E (in other words, switch model) operating point.
Figure 6 shows the simulation results with output time-domain waveform shown versus input drive level. From this figure you can see the output begin to hard compress after about +5-dBm input power.
Figure 6: The time-domain load waveform from the harmonic balance simulation of the PA circuit. Each waveform represents a different power level from the simulation. At +10-dBm output, the amplifier is compressing hard.
Figure 7 is a table of simulation results showing drive level, output power, and PAE. A drive level of +10 dBm was established as a compromise between PAE and the input drive level needed to place the PA into hard compression over all intended drain bias conditions.
Figure 7: Simulation results showing power gain and PAE. Note that at + 10-dBm output, the operating efficiency is at 65 percent while the output power is into 3-dB compression.
Polar Template For PA Verification
Using the PA design in Figure 5 and the earlier ideal polar simulation schematic as a template, the performance of this PA design was established using the polar linearization simulation technique.
To accommodate this analysis, circuit/system co-simulation was used. The AM and PM components of an ETSI EDGE waveform were created in the signal-processing environment. These two components were used as stimuli for the PA circuit-level simulation. The AM component modulates the PA output drain voltage while the PM component is used as an RF drive waveform at the PA input. The modulated performance of the PA design was evaluated using the circuit envelope simulator that allows analysis of non-linear circuits with time varying EDGE waveform.
Before actually modulating the PA drain bias with the AM component, an ideal voltage multiplier model was used to evaluate the basic RF performance of the PA using this template. This intermediate step was performed to validate the simulation template, while using the actual PA circuit in the simulation.
The PA output and AM component were combined as inputs to the ideal voltage multiplier. The output represented the reconstructed waveform.
As shown in Figure 8, the output spectrum and error vector magnitude (EVM) of this system shows that the design concept easily gives acceptable performance, with margin. In this configuration, the PA is driven with +10 dBm as noted earlier, driving the PA with the PM component as a modulated RF signal. The operating efficiency of the PA under these conditions is around 60 percent while still meeting the required ETSI specifications.
Figure 8: The output spectrum and EVM results for the PA design.
As a final proof of PA performance using the polar linearization concept, a simulation template was created to modulate the drain bias of the PA circuit. To do this, the earlier simulation template was modified to include a Class D bias modulator in the AM component path, along with a variable-gain DC amplifier to set the drain bias and subsequent output power.
The Class D modulator basically consists of an integrator and one-bit quantizer in a simple, first-order feedback loop similar to a one-stage sigma-delta modulator. This network allows for very efficient control over drain bias with lower power dissipation than is normally associated with high-current linear bias configuration.
Figure 9 shows the Class D bias network while Figure 10 shows the complete polar template. Note the additional delay element that was added into the PM component path to correct for the delay in the Class D bias network. Figure 11 (below) shows the output spectrum relative to the ETSI mask along with the EVM performance of the final design.
Figure 9: Schematic of the class D bias modulator (delta modulator).
Figure 10: The top-level schematic polar modulation system with PA circuit and bias modulation.
In Figure 10, the EDGE source and EVM sink are both baseband signal-processing components that algorithmically correct for generating and measuring realistic EDGE modulation waveforms. The amplifier symbol represents a sub-network where the PA from Figure 5 is instantiated. The class D modulator is also a sub-network. Both the signal processing and circuit simulations are run concurrently to produce the result shown in Figure 11.
Figure 11:The output spectrum of the PA with polar modulation via bias modulation.
Wrap Up
Polar modulation is a very useful technique for improving the efficiency and stability of a wireless transmitter when size and battery life is important. The performance of a typical PA design was evaluated using the polar technique. The magnitude and phase components of an EDGE 3/8-DQSK waveform were then used as a stimulus for PA circuit-level simulation. The modulated performance of this PA was evaluated and shown to meet the ETSI requirements on both output RF spectrum (ORFS) and error vector magnitude (EVM).
Reference
1. David Su and William McFarland, "An IC for Linearizing RF Power Amplifiers Using Envelope Elimination and Restoration," HPL-98-186.
About the Author
Frank Ditore is a senior applications engineer at Agilent Technologies. He received his BSEE from Newark College of Engineering, NJIT. Frank can be reached at frank_ditore@agilent.com.
