With its picoArray, picoChip joins companies such as Morphics Technology Inc., Intrinsity Inc., QuickSilver Technology and Silicon Access Networks Ltd. in vying for an elusive share of a 3G basestation market yearning for architectural change in the face of unprecedented cost, performance and flexibility issues.

"The basestations in the market today are nowhere near up to production grade in terms of cost," said senior research analyst Sean Lavey at International Data Corp. "Most of the 3G equipment being sold in Japan by NEC and Fujitsu, and even the first few systems being deployed in Europe, are heavily built on FPGAs and are being sold at cost and sometimes even at a loss. Something has to change dramatically to get the costs down, and this [the picoArray] could be it."

Waving 100x deterministic performance, reprogrammability, scalability and a single, completely integrated C-based development environment, picoChip hopes to step up to the onerous baseband-processing requirements of 3G wideband CDMA (W-CDMA) basestations. Such basestations will account for one-third of a baseband signal-processing market that this year is estimated at upwards of $660 million, according to Jim Gunn, an associate with research firm Forward Concepts Inc. (Tempe, Ariz.). Gunn predicts the total market will exceed $950 million by 2006.

The high stakes are both the attraction and the problem for upstarts such as picoChip. With so much at play, there is zero likelihood that incumbents such as Texas Instruments Inc. will readily relinquish their hold on top-tier infrastructure providers. "Companies such as TI are very aware of the problems of applying [DSP-, FPGA- and ASIC-based] 2G architectures to 3G," Lavey said, adding that TI is likely hard at work on processors and architectures that will be up to the task.

But to date the main obstacle for upstarts such as picoChip, according to Forward Concepts' Gunn, has been overcoming the in-house development teams of OEMs such as Ericsson, Nokia, Motorola and Lucent.

That could be changing, however, in the wake of downturn-driven layoffs that have left "many of these companies . . . somewhat resource-limited," said Gunn. As OEMs prove "more open to people coming from the outside," he said, companies like picoChip "will have a better chance at the market from that aspect, though there will be some reluctance and some foot dragging."

Aiming big

Indeed, a recent 3G report from Forward Concepts documents network-equipment vendors' increasingly receptive view of third-party semiconductor intellectual-property suppliers. Nonetheless, picoChip and its fellow startups must still beat the incumbents to design wins with the large telecom vendors if they are to prove their viability.

To seal that first deal, picoChip must pursue a different route than the one taken by its array predecessors. All have promised gobs of compute power and the software flexibility such power entails. The failure modes of their approaches have generally fallen along three lines. The first occurs when the really hard nut is an inner loop that cannot be parallelized and is too tough for any one processor. Second, if parallelization is accomplished, interprocessor communications becomes the bottleneck, and the array can't finish the job fast enough. Third, in the real world (with its asynchronous interrupts and changing task mixes), reconfiguring the array becomes a real-time computing task rather than a design problem, and the approaches fail to compute an optimal array configuration in real-time.

To avoid those pitfalls, picoChip took a radically different approach, said president and CEO Rodger Sykes. "We focused on the specific baseband algorithms of a W-CDMA basestation and then laid out the array accordingly, in terms of the type of processing element and its support structure, memory and interconnection requirements, to optimize for data flow and control."

The result is an array of 430 heterogeneous processing elements that share a common C-compilable instruction set and are roughly the equivalent of an ARM9 in terms of processing power. Each is clocked at 160 MHz and implements three instructions per clock cycle. The array is interconnected by a proprietary 5-Gbit/second bus structure.

The picoArray comprises 430 ARM-like processing elements, each with its own memory and math units.

To accommodate the various W-CDMA baseband-processing functions, the processing elements were subdivided into four types, which differ by application-specific instructions and memory support, said Doug Pulley, co-founder and chief technology officer of picoChip.

"The first type has instructions for such functions as spread/despread and acceleration for forward error correction, such as Viterbi and Turbo," Pulley said. "Another type will have a dedicated multiply-accumulate unit, for filtering, etc. . . . These first two have similar amounts of code and data storage."

The third type is similar to the first type, said Pulley, but quadruples the amount of memory for code and data storage, to address such applications as block processing (vs. stream processing). The extra memory also allows a designer to compile more substantive C to the processor, allowing its use for many control applications in the baseband. "Layer 1 systems are incorporating increasing amounts of control, which is most effectively performed by distributing it throughout the architecture," Pulley said.

The fourth processing element is a form of device controller, so it quadruples the memory yet again. It is used for scheduling operations, Pulley said.

"The key is the mix of processors and how they're laid out," said Rupert Baines, vice president of marketing at picoChip. "It's patterned to suit the way data flows according to the standards and to optimize control of the array." The end result is a "coarse-grained" processor array that picoChip places somewhere between the "fine granularity" of FPGAs and the "big chunks" of a DSP.

Value-add environment

But the path to success for the picoArray doesn't lie solely with its processing capabilities. Much of picoChip's value-add resides with its tools and development environment, said Sykes.

While the processors are coded individually by the designer, said Pulley, "the tools themselves manage the mapping of the code to individual processors and allocate the bus bandwidth in a deterministic way. All the interconnection is determined at compile time, versus run-time, so that you have the guaranteed resources."

With other signal-processing devices, he said, "you end up statistically profiling performance because you don't know what combination of things can occur at once and hence [don't know] what the system load is." Determinism is a plus when doing system-regression testing or verification of individual and composite blocks, he said, since it ensures that resources are available and that bus access is reserved for data transfer between processors.

Also, because of the repetitiveness of communications tasks, the processing capacities defined throughout the array can be replicated many times over, Pulley said. "The chips can be cascaded, and the tools see it as one big array with some constraints at the interconnect points."

PicoChip also provides libraries of functions to allow reuse of the system-level functionality, said Baines, who pointed to the almost homogenous feel of the development environment. "We're providing a much higher level of abstraction from the silicon than, say, you'd have with FPGAs. It also replaces what you'd normally do using both an FPGA and a DSP. Now they're designing for a single processor — albeit many hundred, in an array."

The combination of processing-intensive array, design flow and tools will dramatically reduce the cost of a basestation, reduce development time, enable field upgrades and support operators in field capacity reconfiguration, according to Sykes. "Manufacturers can deliver a flexible product," he said.

The picoArray has been implemented on a 0.13-micron process at Taiwan Semiconductor Manufacturing Co. and is currently in the fab. The company expects first silicon in the next couple of weeks, at which time it can begin characterization.

Pulley said that, based on the design, he expects the chip to support 64 Universal Mobile Telecommunications System voice channels with eight or nine lumped devices, including such advanced "production-ready" features as random-access preamble detection and channel estimators — "basically, all the nasty stuff you need to make it work in the real world."