The melding of in-system serial backplanes and intersystem box-to-box interconnects is becoming clearer at speeds above 3 Gbits/second, courtesy of the design plans of several semiconductor manufacturers. Developers of physical-layer serializer/deserializer (serdes) chips are finding similar issues that drive designs in chip-to-chip interconnect, backplane links between line cards and longer-haul interconnects that link equipment across a rack or a room.
The sweet spot of design resides between 2.5 and 10 Gbits/s, a range that takes into consideration upgrades from existing backplanes and systems that use 10-Gbit Ethernet as a point-to-point interconnect. While most physical-layer vendors emphasize the use of standard bulk CMOS processes over exotic III-V materials, some use conservative CMOS design rules to offer link speeds of 3 Gbits/s, while others push the edge of CMOS capability by supporting 10-Gbit speeds in a single channel.
An intriguing differentiator for future optimized line-card designs will be the difference between standalone physical-layer serdes chips and the hard macros developed by intellectual property (IP) specialists. Rambus Inc. (Los Altos, Calif.) has become an early entrant by updating its Raser family to include the new Raser X module for 10-Gbit/s links. But several physical-layer chip companies said they expect additional players to challenge Rambus on the IP front.
The next few months should tell how quickly OEMs move to 10-Gbit/s speeds. BitBlitz Communications Inc. (Fremont, Calif.) is sampling a quad-channel serdes, the BBT3410, which implements four separate 3.125-Gbit links in a small 1-watt device, configurable as independent links or as a single 10-Gbit Xaui interface. While BitBlitz has been an active member of the High-Speed Backplane Initiative (HSBI), which is touting 5-Gbit/s interoperable backplane standards, director of marketing Leo Wong said the real drive at BitBlitz is to encourage designers to move to 10 Gbits/s as quickly as possible.
In that case, BitBlitz will have to watch out for newcomer Aeluros Inc., a San Jose, Calif., company founded by Rambus and HotRail Inc. veterans. Aeluros is showing prototypes of a CMOS quad serdes device, capable of supporting four separate channels of 10-Gbit links, for a total aggregate speed of 40 Gbits/s (see Figure).
Developers achieve such speeds in standard CMOS through coding efficiency, using either nonreturn-to-zero methods, such as BitBlitz's BBT3410 and future X100 products, or multilevel signaling, touted by Rambus in the tunable pulse amplitude modulation (PAM)-2 and PAM-4 coding used in the Raser family of IP cores. In fact, Kevin Donnelly, vice president of marketing for Rambus' network interconnects group, said tunable signaling will be a critical feature in allowing for flexible serdes designs in the multigigabit realm.
Despite common signal-integrity and clocking issues that unite chip-to-chip, intersystem and intrasystem serial markets, designers are not yet ready for a single physical-layer device for all applications. In fact, Velio Communications Inc. vice president of marketing Bill Woodruff said designers need more specific feature sets when choosing a serdes for synchronous optical network (Sonet), Gigabit Ethernet or backplane applications. Velio (Milpitas, Calif.) believes in this application optimization despite the fact that the company is one of the founders of the HSBI. The industry is close to common serdes building blocks for serial applications, Woodruff said, but that does not lessen the need for application-specific physical-layer parts like the new VC-1021S for Sonet applications.
Velio is using 2.5-Gbit/s channels in quad devices to build 10-Gbit aggregates for a range of Sonet and Ethernet applications. BitBlitz is taking the channel aggregation slightly higher, as it combines 3.125-Gbit/s channels into a 12.5-Gbit serdes with overhead enough to support forward error correction. The nPower BBT3410 is the first generic serial-link device driving BitBlitz to a common 10-Gbit design strategy, said Wong.
"We fully support HSBI because it leads to an interoperable path to building next-generation backplanes," Wong said. "But the endgame here is 10 gigabits. We want to encourage a move to common 10-Gbit strategies sooner rather than later."
Wong and BitBlitz chief executive Ed Rodriguez are promoting the use of common serial building blocks to link multiple chips on a single board, multiple line cards in a single chassis, or multiple servers and switches within a rack or clustered within a single room. That stated goal echoes with Aeluros, though company chief executive Richard Egan said, "Some serial markets may take more time to come to fruition than others. We see our first market for 10-Gbit as sitting in the optics module on the line side. In those applications, the primary metric is power dissipation, which is why we have optimized our designs for low power."
Aeluros is still several months away from a single-channel serdes chip, but it has elected to enter the development market in an unusual way. The company has built a four-channel "torture chamber" test chip, called Bobcat, that demonstrates four separate 10-Gbit/s channels operating at once. While this test chip theoretically offers an aggregate of 40 Gbits/s in speed, Egan stressed that the first products derived from Bobcat will be single-channel, 10-Gbit parts, since "there is no sense in offering integrated 40-Gbit parts when the demand in network equipment just isn't there."
Aeluros, which counts many ex-Rambus executives among its founders, will take out Bobcat's test structures and have silicon room to spare for adding a variety of functions such as Sonet framing or forward error correction.
Rambus, with its new Raser X hard macro, thinks it will make more sense to offer semiconductor partners an efficient 10-Gbit serdes module and let the licensee decide which functions to add. Pulin Desai, product manager at Rambus, said the flexibility of the phase-locked loop used in Raser X will give a great deal of leeway in deciding what mixed-signal functions to add to a serdes core.
As common serial functions emerge for HSBI, Sonet, 10-Gbit Ethernet and specialized external interconnects such as HyperTransport and PCI Express, the competition at the physical layer will grow louder and more confusing. Both hard-macro and application-specific standard product vendors expect existing players to have strong offerings in this field. Two veteran physical-layer players, Vitesse Semiconductor Corp. and Applied Microcircuits Corp., were stalled temporarily at 2.5 Gbits/s as they shifted from gallium arsenide and silicon germanium strategies to mainstream CMOS, but both are expected to play in several markets in the 3- to 10-Gbit realm.
"There will be several ways to enter the high-speed serial interconnect market," said BitBlitz's Wong. "But the common problems encountered in backplanes and out-of-box serial links will mean that the competition for serdes designs is going to get very interesting."
