DALLAS — Intel Corp. will leapfrog the semiconductor-process industry at the National Fiber Optic Engineers Conference here this week when it announces the convergence of silicon germanium heterojunction bipolar transistors on top of its 90-nanometer strained-lattice silicon process with low-k dielectric layers and RF CMOS capability.
With the debut on 300-mm wafers, Intel believes it holds a trump card for integration in several communications niches. A newcomer to the SiGe game, Intel has caught many incumbents off guard and resting on their laurels in 0.25-, 0.18- or 0.13-micron SiGe process nodes they believe still offer the best balance of cost, performance and integration.
"If it had been anyone else attempting this I would've been very skeptical," said Fred Zieber, president of Pathfinder Research (San Jose, Calif.), referring to the yield, cost, signal integrity, modeling and other issues associated with adding the extra layers and designing with SiGe. "But Intel has been fooling around with SiGe for a couple of years now and has the resources, motivation and financial backing to make it work."
The new D1C process initially was expected to serve optical markets, said Intel executive vice president Sean Maloney, who directs the communications group. But the fallout in the optical industry may cause Intel to emphasize RF integration capabilities earlier. Because the process allows integration of many passives on a core design, including inductors and varactors with high-Q factors, it promises clear advantages for high-integration wireless-LAN media-access controllers/transceivers and multifunction 3G baseband devices.
In mixed-signal applications, the D1C process improves integration of functions by 2.5 times, Intel said. For packet processor or DSP blocks, raw performance is doubled over previous digital CMOS processes at Intel. The digitization of functions is accelerated by allowing more analog functions to move onto the core processing chip, where they can be digitized and collapsed into an overall system-on-chip design. Finally, parallel signals can be collapsed and serialized into a port density for serial signals not seen in any communications-oriented processes to date.
'Hitting mainstream'
But with SiGe, Intel is entering an area dominated by IBM Corp. and populated by what Pathfinder Research's Zieber estimates as 27 other SiGe proponents. These include Agere, Atmel, Conexant, Infineon, SiGe Semiconductor, National Semiconductor and even AMI.
"Just a few years ago, people said SiGe would never take off and now it's hitting mainstream," said Teddy O'Connell, senior manager for RF and mixed-signal strategies and marketing at IBM, which is now on its fourth-generation SiGe process. "But only those with big pockets will be staying around," he added, referring to the investment required in core research as well as accurate modeling, improved yield and reliable design kits.
Deep pockets are no concern for Intel. In addition, only a select few of those incumbents are in as good a position to eat the fruits of their own SiGe process labor as Intel is — and none can do so at 90 nm.
Intel's process has its roots in Giga Group, a developer of advanced bipolar equalizers that Intel acquired two years ago. "Ex-Giga Group engineers are directly involved in initial test runs of the new wafers," said Tony Stelliga, general manager of Intel's Optical Division and director of advanced development in the communications group's CTO office. "Their base was in silicon bipolar, but they understood 40-Gbit signal characteristics."
Stelliga said that the SRAM base of the core digital CMOS process is important as more than just a test vehicle. Because the six-transistor SRAM cell already has been implemented in a 52-Mbit SRAM device, the communications group has the experience in hand to add embedded SRAM to a network processor design. The SiGe process adjunct provides a transistor with toggle frequency close to 100 GHz, though Stelliga said a target of 120 GHz was necessary to terminate a forward-error-corrected 40-Gbit signal.
A thick gate oxide over the base CMOS process allows for lower-power CMOS RF and logic blocks, improving signal-to-noise ratio in RF applications. Then, a deep N-well process is used for integrating RF passives on the wafers. Stelliga said that mixed-signal wireless designs require integration of as many passive devices as possible, since "passives chew up a lot of your real estate and can be the first to dirty your signal."
The process has up to seven copper layers. The top one, combined with a high-resistivity substrate, provides the high-Q inductors necessary for optimized RF performance. Low-k dielectric layers, usually touted for improving memory density, also have the advantage of reducing the size of passive and active RF blocks.
Paul Kempf, chief technology officer and vice president of engineering at Jazz Semiconductor Inc., a Newport Beach, Calif., specialty semiconductor wafer foundry company, got a sneak preview of the paper that Intel intends to present on its technology at the International Electron Devices Meeting in San Francisco, Dec. 9-11.
"It's very impressive," he said, "and has a lot of applicability, especially for high-speed-I/O [10-Gbit] intellectual-property building blocks." But as far as Kempf is concerned, it's a long journey from a good paper to a realizable technology. He particularly cited concerns over process yield and cost/performance points.
Applications abound
Intel has already proven the D1C process' capabilities on the broadband-access front through a serializer/deserializer test chip that went through its fabrication facility in Hillsboro, Ore. Stelliga said that in the near future, Intel could develop a 500-MHz aggregation processor that integrates a small switching fabric for adding and dropping channels, as well as framer and MAC functions on both input and output. The SiGe process, in particular, would allow integration of all analog functions up to the direct optical interface.
"A transceiver module that included indium phosphide, silicon bipolar, gallium arsenide and CMOS might be consolidated down to a 90-nm CMOS-SiGe chip and an indium phosphide front end," Stelliga said.
In wireless realms, the process' ability to meld multiple baseband processors, MACs and RF front ends would exceed what the market might want. Maloney said that several multifunction 802.11x chips would be possible, but that Intel would take a careful look at "the usage-model questions that dictate what makes sense.
"I disagree with the model that says integrate any possible network. We could easily combine 802.11 and GPRS [General Packet Radio Service], for example, but it probably would not make sense in models of how people really use handheld devices," Maloney said.
Technical difficulties
But Intel might also trip over the overarching technical difficulties of SiGe and 90-nm-level integration for wireless. The big issues for wireless mobile devices are breakdown voltages and leakage current, said Mark Jakusovsky, wireless marketing manager at Atmel Corp. "They're looking at very thin gate oxides, thereby dropping the breakdown voltage," said Jakusovsky. "In addition, the lower operating voltage [2.5 down to 1.8 V] lowers the threshold voltage and makes it harder to shut the transistors off. Millions of leaky transistors soon add up to high standby-power losses." This isn't such a big deal for wired networks, but it's a problem for a battery-powered device, he said.
However, other applications could take advantage of the 90-nm process' facility in integrating a variety of on-chip buses with low skews. For a voice-over-Internet Protocol processor, for example, Intel will be able to integrate several blocks in an IXS Media Signal Processor array, under the control of a common host integer processor on the same die.
Mark Bohr, Intel fellow in the technology development group, said the new processes will be implemented solely in fabs using 300-mm wafers. Once the Hillsboro fab is converted to volume production, the 90-nm process will be transferred to fabs in Ireland and New Mexico.
"We originally shot for SiGe at 130 nm, but found that the time it was taking to develop it was overlapping with the introduction of the 130-nm process," Bohr said. "So we shot a bit higher, for 90 nm, to give us more time and coordinate it better."
To get there, he said, "We had to come up with a simple and straightforward HBT process that doesn't incur too many more steps and doesn't interfere with the digital CMOS process. Digital CMOS is very sensitive to wafer process temperatures, so we had to reduce both the temperatures involved and the number of steps." Bohr's group has been working on SiGe processes for two years, and was able to implement an HBT-based process using up to 30 percent fewer process steps than competitors.
But Kevin Kolwicz, director of technical strategies at Agere Systems Inc., was not impressed. "At 90 nm you're looking at eight-level metal layers, requiring 30 to 35 masks — you add 30 percent more steps for SiGe and that amounts to roughly 10 more steps," Kolwicz said. "That adds to cost pretty fast." Agere has been working with low-cost SiGe for a number of years and is now at 140 nm and 120 GHz, with wireless as its target.
