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06 July 2009



Bay stresses internetworking in 10-Gbit processor

By Loring Wirbel
Courtesy of EE Times
Apr 15, 2002
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SANTA CLARA, Calif. — Bay Microsystems Inc. this week will sample its long-promised Montego network processor, a 10-Gbit/second deterministic pipeline device in which service interworking and channelization play a central role. Along with its embedded processor, Montego features an embedded 32-Gbit/s switching fabric to support its use in aggregation and edge-switching systems.

Aggregation has escalated in importance since the incumbent local-exchange carriers (ILECs) have won the lion's share of the carrier business, said Chuck Gershman, senior vice president and co-founder of Bay Microsystems. "Pleasing the ILECs means handling legacy traffic," he said. "If we saw an all-IP Internet Protocol network emerging, we wouldn't have spent so much time on features like VC virtual channel mapping or microflow mapping."

Montego's guaranteed support for 10-Gbit/s wire-speed networking applies even when mixes of ATM, packet-over-Sonet, frame relay, Ethernet and IPv4 traffic are encountered. Bay specifies a packet-processing rate of 31.25 million packets/second and a packet search rate of 83 million packets/s. In fact, the pipeline can operate at up to 41.25 million packets/s but is limited by the bandwidth of the memory bus.

Bay has always argued against nondeterminism in cases where fine-grained quality-of-service must be supported. Gershman said Montego's deterministic pipeline mandates that operations on a particular header field be completed within a certain task window, giving the processor better control over flows, particularly when pipelines must handle mixes of IP packets and ATM cells.

The AnyMapping forwarding feature allows forwarding and bridging at line speed, including support for all operations, such as cyclic redundancy checks, time-to-live and checksum operations. The design team at Bay took the time to create a complex forwarder, Gershman said, adding, "Intelligent forwarding is the bane of most my competition."

Montego's on-chip classification engine can interface to CAM-based lookup tables and will be expandable in the future from 83 million searches per second to 300 million searches/s.

One important design target for the single-chip device was the ability to support 64,000 virtual channels, or 4,096 media ports across 16 physical channels. Whether access systems are designed for cable modem termination systems or telco central-office multiplexers, the density of ports planned for many systems requires such granularity, Gershman said.

Bay is bringing Montego to market with a full internetworking development system based on VxWorks. In its first instantiation, the IDS is offered as a single line card, the IDS-10G, but the company also plans a system-level development system, the IDS-80G, which will support up to eight line cards with a unified switching fabric.

Both versions will come with the Network Engine XTension (Nextware) software suite and a Cycle-Accurate Simulation Environment (Case) C environment. The latter allows modeling of the Montego processor's cycles and pipelines, including both instruction and data flows.

The Nextware software, provides high-layer application programming interfaces and a library of application layer modules. The software eliminates the need for a device-level operating system for the network processor. Users can interact with the development system using Java GUIs, a command-line interface, an API suite or direct drivers.

Bay will offer Montego at a volume price of less than $1,200. The processor is packaged in a 1600-pin BGA epoxy flip-chip and will move into full production by the third quarter.




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