CommsDesign Apr 10, 2002

The AmberBridge HyperTransport physical layer (PHY) core has been unleashed for communication chip designs. Targeted at 0.13-micron processes, the core delivers an aggregate bandwidth of 12.8 Gbps. The core sports three components: a transmitter, a receiver, and an impedance calibrator. The core also provides embedded testability features. The core complies with version 1.01 of the HyperTransport PHY interface spec and version 1.03 of the HyperTransport I/O link protocol specification.

Availability: Now

NurLogic Design, www.nurlogic.com