SAN MATEO, Calif. — In a move that could spark controversy, the Network Processor Forum has picked a modified version of System Packet Interface 5 as a standard high-speed interface to link co-processors and memory chips to future network processors supporting transfer rates of 10 to 40 Gbits/second.
The decision could mark a setback for net processor vendors, including Broadcom Corp. and PMC-Sierra Inc., that have committed to using the Hypertransport interface for their NPUs. It could also set off a scramble among networking chip vendors to master the sometimes complex analog serializer/deserializer (serdes) technology on which SPI-5 is based.
Indeed, the move has already raised the hackles of some engineers, who said SPI-5 could draw too much power for memory chips.
The Network Processor Forum's efforts on the Look Aside-2 (LA-2) interface have been closely watched by makers of network processors and of content-addressable memories. At least five parties, including Intel Corp., members of the Hypertransport Consortium and Cypress Semiconductor Corp., submitted proposals on the standard in the fall.
A spokesman for the Hypertransport group said the communications-specific extensions to LA-2 that it proposed under a nondisclosure agreement will still come to market as part of a broad Hypertransport 2.0 spec this fall, even if the forum does not adopt its proposal.
The Hypertransport group proposed what it calls network-centric Hypertransport, extensions that would provide more error correction, larger packet size (about 256 kbytes, up from 64 kbytes) and other features the group is still keeping under wraps. The exact feature set is still being debated with working members that now include Broadcom, PMC-Sierra, Cavium Networks and Cisco Systems.
The networking extensions, along with cache coherency to support multiprocessing computers and a speed bump from the current 1.6 Gbits/s to between 4 and 6 Gbits/s, are expected to be wrapped together as part of Hypertransport 2.0, to emerge this fall.
In a Network Processor Forum committee vote conducted March 1, a SPI-5 proposal from AMCC, Agere Systems and CAM vendor Sibercore was selected as the baseline spec for LA-2. The proposal is expected to face possible modifications before a final forum ballot on the spec this fall. SPI-5 is itself still in a proposal stage as a high-speed interface at the Optical Internetworking Forum (OIF), which defined its predecessor, SPI-4.
The SPI-5 proposal for LA-2 requires such features as a phase-locked loop and clock data recovery. Taken together, those features could eat up 3.5 to 4 watts, according to one source familiar with the LA-2 discussion who asked not to be identified.
"The power dissipation is unacceptable for SRAMs, which have a total 1-W power dissipation today. There needs to be some kind of overall cost reduction of the interface here," said the engineer. There was "quite a bit of dissension" over the SPI-5 vote, he added.
Serdes technology represents the best choice for the high-speed NPU interface because its message-passing, 3-Gbit/s bandwidth per pin will keep processors in a single-chip package. That's more important than any design changes SRAM makers face, said David Sonnier, chief technology officer for network processors at Agere Systems (Austin Texas), which co-sponsored the SPI-5 proposal. Actual power consumption of serdes interfaces can be less than 2 W, he added.
"If you kept SRAMs down to 1 W but had to split the network processor up into five chips because you were pin-limited, would you be better off? This is the battle of the trade-off," Sonnier said. "We have to think of the size and power considerations at the systems level."
With the exception of a few companies, such as Agere and AMCC, the SPI-5 interface will create design challenges for most NPU makers, said Bob Wheeler, an analyst for The Linley Group (Mountain View, Calif.).
"Most vendors have been shying away from SPI-5 because the OIF standard hasn't been solidified yet," Wheeler said. "I think it will be fundamentally new technology for all the co-processor vendors. I don't think it will be a big advantage for anyone."
But Wheeler and Sonnier both noted that a handful of companies, such as Nurlogic Design Inc. (San Diego) and Rambus Inc. (Los Altos, Calif.), are licensing their serdes technology and could see an uptick in business following the vote.
"We are getting a lot better at building serdes as an industry," said Sonnier. "Power has been coming down about 50 percent a year. Now there will be an even bigger push to get that technology improved. A lot of people still consider it black magic." He noted that Agere already has embedded serdes links to its in-house switching fabric.
The LA-2 proposal uses a modified version of SPI-5 that adopts 8b10b coding to assure smooth transitions between data rates without losing packets. In addition, the LA-2 group decided to overlay an encoding scheme presented by Cypress on top of the physical layer SPI-5 proposal.
The LA-2 spec is designed as a high-speed upgrade for the existing LA-1, which specifies for OC-48 (2.5-Gbit/s) systems the quad-data-rate (QDR) interface already used in SRAMs today.
"The market downturn is actually good for the LA-2 standard," said Sonnier. "If the market was going gangbusters, you would have seen all sorts of people doing ad hoc designs because people needed a part. Now, whenever the market accelerates, there will be a standard in place."
