Each of these criteria has a direct impact on the decision a designer will make when choosing a DSP, ASIC, or FPGA.

Programmability

DSPs and FPGAs can be easily reconfigured to fulfill a variety of functions in a software-defined radio design. Off-the-shelf communication ASICs, while often providing better performance at lower cost, offer only limited programmability.

The question is whether one of the wide variety of wireless ASICs available are appropriate for a particular digital radio product. In a pure software-defined radio architecture the answer would obviously be no. But only a few digital radio designs actually require this level of flexibility. As such, a major step in the development of any new software-defined radio (SDR) product is to determine the programmable features required in each function of the system. This evaluation can then be used to qualify whether an off-the-shelf ASIC can be considered for that function.

Determining processing functions can be illustrated by considering a base station transceiver architecture supporting both wideband CDMA (W-CDMA) and GSM. W-CDMA uses a spread-spectrum communication technology with dozens of users sharing a single RF channel. The W-CDMA signal occupies 5 MHz of bandwidth per channel, between 1920 and 1980 MHz for the uplink and 2110 and 2170 MHz for the downlink.

GSM, on the other hand, employs a narrowband TDMA technology typically supporting only eight users per RF channel. This technology occupies a 200-kHz bandwidth per channel between 890 and 915 MHz for the uplink and 935 and 960 MHz for the downlink.

To accommodate these divergent standards in a software-defined architecture, the digital upconversion and downconversion components of the IF processor must provide programmable channel selection, filter setup, and sample rate adjustment. New multi-standard digital transceiver ASICs from Intersil, Graychip, and Analog Devices provide many of these programmable features.

For example, the Graychip GC4016 digital downconverter can be reconfigured as either a four-channel narrowband downconverter with a maximum useable baseband bandwidth per channel of 2.25 MHz, or a single-channel wideband downconverter with a maximum useable baseband bandwidth of 9 MHz. 2 In addition, the GC4016 supports a user-programmable baseband filter and a user-programmable re-sampler in each channel, making the device suitable for IF processing in the defined architecture.

If, however, the device included a requirement to support a future upgrade to an as yet undefined fourth-generation (4G) wireless architecture, the applicability of an ASIC in the digital radio design changes. For example, there has been a good deal of talk in the wireless market about employing orthogonal frequency-division multiplexing (OFDM) in 4G system architectures because of its robust performance in a multipath environment and its compatibility with broadband standards such as local multipoint distribution service (LMDS) and multichannel multipoint distribution service (MMDS). However, since 4G standards are still not defined, the use of any ASIC signal-processing device in this architecture represents an unacceptable risk in insuring the future upgrade, and thus an FPGA or DSP must be used for the IF processing.

The farther the signal processing is from the digital IF input, the more specialized the processing algorithms for the architecture become, limiting the likelihood that a single ASIC device can meet the required programmability criteria.

In the 3G/GSM radio example, W-CDMA employs an error correction scheme consisting of a combination of turbo coding and convolutional coding to achieve the required BER performance. GSM, on the other hand, uses a combination of convolutional coding and fire coding as its error correction scheme. As such, the use of a commercial ASIC targeted at a specific error correction algorithm would be inappropriate for this platform, and an FPGA or DSP implementation would be a better choice.

Integration chronicles

Level of integration is another area where ASIC devices are at a disadvantage in software-defined radio architectures. As the technology involved in the development of ASICs, DSPs, and FPGAs improves, the number of simultaneous functions that can be integrated into a single device increases dramatically. For an ASIC, however, as the level of integration increases, the flexibility of the ASIC decreases.

For example, an ASIC chip de-signed to act as a digital transceiver may be perfectly suitable for multiple air interface standards, including GSM, IS-136, cdma2000, and UMTS W-CDMA. If a CDMA chip rate processor is added to this ASIC, then it is no longer suitable for GSM and IS-136. Add a modulator/demodulator supporting QPSK, 8-PSK, and 16-QAM modulation schemes, and the chip becomes an efficient solution for implementing the cdma2000 high data rate (HDR) specification, but is not usable for any other standard.

At this level of integration, multiple ASIC devices would be needed to support multiple air interface standards, which is often impractical.

In contrast, multiple digital radio functions can be easily integrated into a DSP or FPGA device without a significant loss of flexibility.

In the example above, most of the functions provided by the cdma2000 HDR ASIC can be implemented in a Xilinx XCV1000E, as shown in the Table 1. This level of integration often leads to products with a smaller overall form factor and more available features than the ASIC-based equivalent.

Table 1: Implementation of a CDMA 2000 HDR Radio on an FPGA
Function	Configurable logic block slice estimation
DDS [3]	67
Mixer [3]	202
Filtering (dual 49 tap FIR) 3	3936
User detection 4	1118
Carrier and clock recovery5	2000
Symbol/ bit mapping	800
Miscellaneous	1000
Total	9123 (~ 74% of XCV1000E) 6

Development cycle

The reduced flexibility of an ASIC device does offer one advantage in the development of software-defined radio products: algorithm development for an off-the-shelf ASIC is already complete which allows a faster time to market. The critical development path for an ASIC-based function is the hardware design, with the software development limited to the creation of a library to access the programmable features of the device.

The development cycle for a DSP or FPGA-based design is much more involved, with software development often requiring more resources than the corresponding hardware development effort. Off-the-shelf libraries of optimized general-purpose algorithms are often available for both DSPs and FPGAs to accelerate this process, however these algorithms must be integrated together to implement the desired digital radio function and thus require a full software development cycle.

It should be noted that there is a major difference in the way in which software is developed for DSPs and FPGAs. The time it takes to compile an algorithm on a DSP is typically measured in seconds, whereas the time to synthesize and route a similar algorithm on an FPGA may encompass hours. Xilinx, for example, advertises typical routing times of around 400,000 gates per hour.7 The compilation of a large design filling a 2 million gate XCV2000E could therefore take half a day.

This makes design debugging a more costly process on an FPGA. As such, FPGA design cycles usually involve more up-front analysis, including the development of multiple simulation and test models, before routing of the algorithm to the device ever takes place.

Performance

Qualification of any signal-processing device considered for use in software-defined radio architectures must include an evaluation of whether the device can perform the required functions in the specified time. One of the basic benchmark measurements used in this type of assessment is the processing time required for a 1024-point Fast Fourier transform (FFT). This time is highlighted in Table 2.

Table 2: Processing Time Required to Perform a 1024-Point FFT
Device Type	Manufacturer	Device	Clock speed (MHz) (sec)	Time for 1024-point FFT
DSP8	Texas Instruments	TMS320C6203	300	43.2
FPGA9	Xilinx	XCV300E	100	41.0
Programmable ASIC10	Catalina Research	TMS320C6203	133	15.4

In the example highlighted in Table 2, the programmable ASIC from Catalina Research clearly outperforms the DSP or FPGA implementation. ASICs in general offer the highest level of performance for any given function, with the execution time for that function stated on the data sheet.

Comparing the performance of a DSP and FPGA implementation of a function can be challenging, because the architectures of these devices favor different types of problems. DSPs operate at very high rates but are limited to performing only a few operations at a time. FPGAs on the other hand, typically operate at slower speeds than DSPs, but allow an almost unlimited number of operations to occur simultaneously.

To illustrate these differences, consider the simple 16-tap FIR filter shown in Figure 2. This filter requires 16 multiply-and-accumulate (MAC) operations per sample. A Texas Instruments TMS320C6203 DSP clocked at 300 MHz can provide around 400 to 500 million MAC (MMAC) operations per second in a reasonably optimized design. This means that a 'C6203 device can implement the FIR filter at a maximum input rate of around 31 MSamples/s.

In an FPGA, however, all 16 MACs can occur in parallel. For a Xilinx Virtex part, a 16-b MAC requires approximately 160 configurable-logic-block (CLB) slices to implement, and so a design implementing 16 simultaneous MAC operations would require approximately 2560 CLB slices.11 This can easily fit into a XCV300E, which will allow the FIR filter to operate at input sample rates of over 100 MSamples/s.

Power pluses

ASIC devices are generally optimized to provide outstanding power performance. The power requirements of most programmable devices, however, increase substantially with device utilization and clock rate, and this must be taken into account when evaluating the power budget for the overall design.

For example, a four-channel downconverter implemented on an Altera 20K600 programmable logic device (PLD) draws less than 2W of power for input data clocked at 25 MSamples/s.12, 13 This level is high but may be acceptable for the given application. By increasing the input rate to 65 MSamples/s, however, the power draw grows to around 5W, which may stress the power budget of many digital radio products.

In contrast, the AD6624 four-channel downconverter ASIC from Analog Devices dissipates around 700-mW power when clocked at the same rate.

At lower rates, the power utilization of an FPGA is often superior to that of a high end DSP. To illustrate this, consider the error correction scheme used by the Dish Network for digital video broadcast.14 In this system, multiplexed data at up to 27.647 Mbps is encoded using a Reed-Solomon error correction scheme. This scheme generates 16 parity bytes for every 188 data bytes, creating a maximum composite data rate of 30 Mbps.

A TMS320C6203 can decode the 204-byte Reed-Solomon codeword in under 5000 cycles.15 To achieve the required throughput, at 300 MHz the CPU must operate at about 50% utilization, which requires approximately 1.53W of power.16 In contrast, an off-the-shelf Reed-Solomon decoder design implemented on a Xilinx XCV 100E dissipates less than 200mW power.17,18 This is a substantial improvement, and is comparable to the performance that would be achieved with a commercial Reed-Solomon ASIC, such as the AHA4011C from Advanced Hardware Architectures.19

Device selection

Table 3 summarizes the topics covered above. In this table, the devices are subjectively rated on a scale of 1 to 5 for each category, with a 1 indicating a poor choice for that category and a 5 indicating an outstanding selection.

Table 3: Rating the Components
Evaluation category	COTS ASIC	FPGA	DSP) (sec)
Programmability	1	4	5
Integration	2	5	5
Development	5	1	3
Performance	5	4	3
Power	5	2	3

With the above analysis in mind, several general guidelines can be developed for the partitioning of a software defined radio design between ASIC, FPGA, and DSP devices. These guidelines can be summarized as follows:

• ASICs typically offer the best solution for a given function, if they provide an acceptable level of "programmability" and integration.

• FPGAs provide the best programmable solution for high-speed signal processing functions that are highly parallel or involve linear processing.

• DSPs provide the best programmable solution for functions that involve complex analysis or decision-making.

Going forward, DSPs ASICs, and FPGAs will continue to support more functionality on chip, blurring the line between these products even more. To the software-defined radio designer, this means that the headaches will continue to grow as time goes on.

Lee Pucker is a systems architect in the wireless systems business unit at Spectrum Signal Processing, Inc. He received his BASc degree from the University of Illinois, and his MSEE at Johns Hopkins University in 1991. He can be reached at lee_pucker@spectrumsignal.com.

References