Freescale will show its first dual-core PowerPC this week at the Smart Networks Developer Forum Europe. The PowerPC will integrate a system controller and interface bus borrowed from the company's earlier PowerQuicc families. In fact, the new dual-core MPC8641D and single-core MPC8641 will use the same internal buses and peripherals leveraged from PowerQuicc, but the former device will use dual e600 cores that can be employed in either symmetric- or asymmetric-multiprocessing domains.

In the PowerQuicc III family, four new processors will be shown that employ the same internal MPX bus used in the dual-core PowerPC: the MPC8548E, for telecom and networking applications; the MPC8547E, for storage; the MPC8545E, for imaging; and the MPC8543E, for general control applications.

Rounding out the series will be the MPC7448, a single-core upgrade from the MPC7447A. This device borrows the system controller from the PowerQuicc but does not offer the PowerQuicc's multiple Gigabit Ethernet controllers and multiple serial I/O options, which are offered in both the MPC8641 and the MPC8641D PowerPCs.

The trading of design methodologies and features indicates the growing overlap between embedded PowerPC and PowerQuicc applications. Whereas the PowerQuicc once was characterized by multiple peripherals optimized for communications, both families now feature common peripheral sets. For example, the Gigabit Ethernet MACs used in both families have been upgraded. They offer support for Internet Protocol header checksums; TCP and UDP payload checksums; and dedicated quality-of-service features, such as eight hardware queues for both transmit and receive and 256 rules for performing packet parsing.

"There is a common base of system applications, some of which are strict data path-emphasizing speeds and some of which combine control plane and data plane in one line card design," said Toby Foster, system architect for the e600 PowerPC core at Freescale, which was spun out of Motorola Inc.'s Semiconductor Products Sector earlier this year. "We consciously went with shared system-on-chip modules, and even common pinouts, across different family members to make it simpler for customers to create a family of system designs with different performance levels and price points."

The 8641D replicates more than the e600 core itself. The chip has two 1-Mbyte Level 2 caches and dual AltiVec vector-processing engines. Like the PowerQuicc, the 8641 (in both single and dual versions) turns the MPX bus into a fully internal bus for faster access between core processor and peripherals. In the 7448, as in previous 7xxx family members, the MPX bus is an external bus with interface pins to separate devices.

The PowerQuicc III derivatives have some features specific to target markets, said product-marketing manager Lakshmi Mandyam. The 8548E offers support for Kasumi encryption used in third-generation applications; thxe 8547E has an exclusive OR block for dual parity operations in RAID storage; and the 8545E supports double-precision floating-point operations for imaging.

All versions of the PowerQuicc III have a 512-kbyte L2 cache, an integrated security engine and support for DDR-II and SDRAM-II memory interfaces.

Recognizing the different applications for PCI Express and serial Rapid I/O, the PowerQuicc and PowerPC families offer choices for serial interfaces. Designers can implement single-lane or quad-lane serial Rapid I/O v1.2 as a board-to-board or backplane interconnect. At the same time, they can implement x1, x2, x4 or x8 PCI Express interfaces at 2 Gbits/second per link. Each PCI Express interface can be configured as a root complex to be used with a bridge to peripherals or as a direct peripheral endpoint.

All processors except the 7448 will ship in a 960-pin HiTCE ceramic package, with the 7448 in a 360-pin BGA. The 7448 will sample in the first half, with PowerQuicc members slated for the second quarter, and the single- and dual-core 8641s will sample in the second half of 2005.