With the development of next-generation mobile communications, IrDA technology has emerged in mobile phones, PDAs, and digital cameras, along with traditional portable PCs and printers. The industry needs a higher data rate above 1 Mbps for 3G wireless communication protocols, such as W-CDMA. Agilent Technologies, as a principal member of IrDA, has been developing a low-cost and higher speed IR transceiver for mobile communication needs. An increase in the encoded infrared data rate over 1 Mbps would allow a flow of 3G data from the cellular network, through a handset, to a laptop, PDA or other peripherals, such as a printer. The current objective of our design is to provide a means for low-cost and point-to-point communications between computers and mobile devices such as PDAs and mobile phones in medium infrared (MIR) mode, using directed half-duplex serial infrared communication links through free space.

IrDA Protocol

IrDA Objectives
When IrDA was established, its main objective was to create an interoperable, low-cost infrared data interconnection standard supporting a walk-up, point-to-point user model. The standard should be adaptable to a broad range of mobile appliances that need to connect to peripheral devices and hosts. To target such a broad range of devices, the following set of requirements was placed on IrDA:

• Low cost
• Industry standard
• Compact, lightweight, and low power
• Intuitive and easy to use
• Non-interfering

Using these requirements, the IrDA committee developed a series of standards aimed at providing common, low-cost, directed infrared communications for all classes of mobile computing devices.

IrDA Architecture

Figure 1:  IrDA protocol architecture

IrDA has defined an interface for infrared communications that consists of several layers (Figure 1). These three layers—IrPHY (Infrared Physical Layer), IrLAP (Infrared Link Access Protocol), and IrLMP (Infrared Link Management Protocol)—form the core of the IrDA architecture; all are required for a device to be IrDA-compliant.

IrDA defined four kinds of infrared links to support different data rates. Included in these links are Serial Infrared (SIR) supporting speeds up to 115.2 Kbps, Medium Infrared (MIR) supporting 0.576 Mbps and 1.152 Mbps data rates, Fast Infrared (FIR) supporting a 4.0 Mbps data rate, and Very Fast Infrared (VFIR) supporting 16.0 Mbps.

In addition to the base standards, IrDA has specified several optional layers such as Tiny TP, IrCOMM, and IrOBEX. Developers can build applications on top of these layers, as shown in Figure 1.

System Architecture

The IR controller system architecture is shown in Figure 2. The system includes the following blocks: core control modules, clock generator and distribution, DMA control, FIFOs, ISA interface, and modulation/demodulation modules for all the operating modes. We designed all the modules in Verilog and discuss some of the modules in detail in the following sections.

Core Control Module
We designed five state machines to transmit and receive data in different modes. All the state machines perform parallel-to-serial conversion on the transmitter side, and serial-to-parallel conversion on the receiver side. On the transmitter side, the corresponding frame is generated with the payload data. On the receiver side, the incoming frame is examined and the payload data is extracted and saved into the RX_FIFO. If an error occurs, an interrupt signal will be asserted if the signal is enabled. This controller supports SIR, MIR and normal UART modes. The framing format varies from mode to mode, as shown in Figure 3. For SIR mode, its frame format is the same as for a UART, which begins with one start bit (logic 0) followed by 8 data bits and optional parity bit(s), and ends with one or more stop bits. This format is called asynchronous format, because only one byte of data is transmitted/received in one frame. In contrast, the MIR format is synchronous format, which is more complicated than asynchronous format. This paper focuses on the MIR mode and synchronous-format design.

Figure 3:  IR framing format

The MIR frame format follows the standard HDLC format except that it requires two beginning flags (STA and '7E'hex), and consists of two beginning flags, an address field, a control field, an information field, a frame check sequence field, and a minimum of one ending flag (STO, '7E'hex). Stuffing/de-stuffing is performed for the payload and CRC fields. This means one zero is inserted after five consecutive ones are transmitted in order to distinguish the flag from data, while one zero is taken out after five consecutive ones when receiving.

Modulation and Demodulation

Figure 4:  IR modulation schemes

The modulation and demodulation schemes for SIR and MIR modes are shown in Figure 4. For SIR, a pulse of 3/16-bit duration represents a zero. An absence of a pulse indicates a one. For example, 3/16 of a pulse width at 115,200 bits/s is 1.6 µs. The code is power-efficient, since infrared is only transmitted for zeros. The tall narrow pulse has a better signal-to-noise ratio than a short wide pulse of the same energy. The MIR modulation scheme is similar to that of the SIR, except it has a pulse width of 1/4 of the bit-cell time.

Transmitter Section
When the transmitter is empty, if either the CPU or the DMA controller writes data into the TX_FIFO, frame transmission will begin. This transmitter section contains several major state machines, each performing its task in sequence for the transmission of a bit-stream. As mentioned previously, different modes require different frame formats. Initial protocol negotiation takes place at 9600 bps, making this data rate compulsory. All other rates are optional and can be added if a device requires a higher data rate.

MIR requires transmission of a 16-bit CRC and beginning/ending flags. This design adopts a parallel method to create CRC and flags in order to maintain data coherency. When the controller reads the 8-bit parallel data from TX_FIFO, the parallel-to-serial conversion will begin at the falling edge of the RD signal. This system uses an algorithm commonly called the Ping-Pong method. Only 2 bytes (two buffers) are used for real-time parallel-to-serial conversion; therefore, the gate count will be significantly reduced after this module is synthesized into the practical hardware. As shown in Figure 5, an RD signal is asserted every eight clock cycles, and one byte in a buffer will be shifted to the subsequent block. In order to avoid overwriting the buffer, you need to exchange data at a previous time point, as shown in Figure 5. When the final data bit passes through the frame assembly block and feeds into the encoding block, the CRC result (16 bits) will be produced during the same clock cycle and is attached to the bit stream to maintain data coherency.

Figure 5:  Parallel-to serial conversion algorithm

For this system, we have adopted a clock divider in this section for a variety of date rates. The oscillator currently has two options, 40MHz and 48 MHz. Dependent on the input (main frequency), the main timing counter wraps around after 34(41) or 35(42) for 40(48) MHz operation. The circuit uses a programmable divider to generate variable data rates in the system. The divider is designed as an array of record elements that, ultimately, contain the bit-rate. The array also contains the minimum, nominal and maximum pulse widths for the bit-rate, and the width of the bit-time in ns or µs. The 'baud_data' array contains elements for bit-rates defined by the Link Access Protocol. A simple choice of bit-rate, by means of a control signal obtained by programming the chip, forces the transmitter or receiver section to get its required data from the 'baud_data' array instead of through calculation. Finally, the section outputs a small pulse at the end of an SIR or MIR transmission based on the prescaled main clock.

Receiver Section
When the receiver front-end detects an incoming frame, it will start de-serializing the infrared bit stream and load the resulting data bytes into the RX_FIFO. Figure 6 shows how the incoming IR signal must pass through a filter first. This module has two objectives—to limit the pulse width of the common IR input to a fixed value (3 chip_clk period in this design), invert the polarity of the input signal, and remove the noise spike from the input signal. The receiver waits for the first following falling-edge of the incoming data stream. This allows calculation of the detected pulsewidth and time to the center of the next and all the following bit-time frames. The receiver interprets the edges and calculations depending on the mode. For an SIR or UART mode, it indicates the leading logic '0' (start) bit for the first byte; in MIR mode, it indicates the leading logic '0' in the 'start-stop-flag' (7E hex). After detecting the correct beginning flag, the receiver will process the consecutive bits in sequence, much like the transmitter; for example, decoding, de-assembly, de-stuffing and doing a CRC check. Subsequently, the serial data are converted to parallel data for writing into RX_FIFO.

Data synchronization and clock recovery are the key parts of the receiver section. During infrared transmission, it is possible to have jitter or pattern-dependent propagation delay problems as shown by the dashed lines in Figure 6. These types of problems mean that sometimes the next IR pulse will be delayed after several consecutive ones (no pulse) occur. In SIR or MIR mode, any rising edge of incoming IR pulses resynchronizes the local clock to the start point, as shown in Figure 6. The recovery clock samples the filtered input data in this design.

Figure 6:  Signal waveform in the receiver section

Meanwhile, this section is responsible for reporting to the upper layer through some signals when errors occur. Among the error conditions this sections checks are:

1. For modes utilizing a parity bit, detect when a parity bit is missing when required, and detect when a parity bit is the wrong value.
   
   
2. For modes that require bit stuffing, detect when those bits are missed or placed in incorrect places.
   
   
3. For modes which utilize a CRC token, detect when the token is incorrect.
   
   
4. All modes will detect when the received data packet does not match the expected data packet, including data length and frame format.

Figure 7 shows signal flow in the receiver section. The 'abort_frame' signal is asserted when any kind of error occurs. This signal disables the serial-to-parallel module and resets the receiving process for the next frame. In addition, error information will be written into the corresponding status register to report to the upper layer.

Figure 7:  Signal flow in receiver section

The system architecture is optimized to meet the requirements of a variety of UART and infrared-based applications. The architecture incorporates DMA support for all operational modes. You need one DMA channel for an infrared-based application, since infrared communications works in a half-duplex mode. In addition, the system uses STC (Serial interface for Transceiver Control). The serial interface is designed to interconnect two or more devices. A set of commands handles the various transactions between the master circuit and the each of the slaves, such as controlling transmitter power level and selecting primary receiver sensitivity.

Design Flow and Lessons Learned

Design Flow
The total design flow consists of several major tasks.

• Design Entry
  This controller was designed in RTL Verilog and then synthesized into actual gates.
  
  
• Design Verification
  You can broadly divide the design-verification process into two parts-functional verification and timing verification. We created several testbenches to test different portions of system functionality. After all the test cases passed without error, we did logic synthesis using Synopsys tools. The synthesis process converts the RTL-level design into a real gate-level design. The timing process at this point refers to gate timing, but does not accurately describe interconnect delays, since we have not yet done chip layout.
  
  
• Design Handoff
  The design-handoff stage involves final design-rule checking, test-vector generation, layout, and post-layout timing verification. If post-layout simulation is error-free, then the design can go to fabrication.

Lessons Learned
The development of the infrared communication controller in Verilog taught us some valuable lessons. For example, the receiver section of this system became very much more complex than the transmitter section. Both sections were allocated equal time for development, but the receiver design effort used the majority of the overall schedule. After project completion, we analyzed why this design-time discrepancy occurred. We came to this conclusion: while the transmitter section could use parameters which were largely unchanging and already known, the receiver section was required to continually test the input stream for pulse widths, calculate sampling periods, and detect error conditions which could not be predicted. The lesson learned here is that the receiver section should have been developed first, and that the receiver should have been given the majority of the development schedule. In addition, developing all kinds of testbenches took more time than originally expected. However, this process is very important to verify system functionality and timing. The danger here is that the design may fail under some other set of operating conditions or circumstances. Simulation is the proper way to catch and correct these potential disasters.

The infrared controller discussed in this article provides a low-cost hardware solution for IrDA 1.x protocol-compatible wireless communications. With the rapid development of next-generation wireless mobile communications, the range of IrDA applications will continue to expand.

References