The need to move large quantities of data at high speeds continues to increase, pressuring component manufacturers to improve their technology and, simultaneously, to reduce costs. One of the key factors in both cost and performance is packaging. Wireless IC and component packaging is undergoing substantial changes in response to these pressures.
Both communications- and digital-IC technologies are moving to progressively higher frequencies. At these higher frequencies, the limiting factor for many wireless components is often the package parasitic effects, not the IC itself. Packaging parasitic factors (physical, distributed, and electromagnetic effects) can limit the frequency response or signal integrity of an otherwise robust circuit design, keeping it from reaching its potential speed of operation.
The value of a packaging solution—in both cost and performance—increases as the frequency of operation increases, becoming a dominant factor for product success at frequencies above 2 GHz. Failure to obtain a packaging solution that meets both performance and cost criteria can contribute to late product introduction or even total market failure.
The value of packaging is especially evident to commercial-volume microwave-component manufacturers, who often find that packaging costs are prohibitively expensive for their applications. Often locked in competitive struggles, these companies seek effective packaging that leverages standard manufacturing processes, providing a way to significantly reduce the cost of their radios and communications equipment. Wireless applications are not the only area where high-frequency packaging can play a key role in product success. High-speed logic, bus transmission, and fiber communications are reaching data rates that dictate the need for a high-frequency, broadband packaging solution.
What Must a Package Do?
A package performs at least eight major functions that need to be understood if its cost and performance are to be improved:
- Protect the circuit/die from the external environment
- Protect the circuit/die during manufacture of the PCB
- Provide a power connection from the circuit/die to the PCB
- Provide an electrical signal interface from the circuit/die to the PCB
- Provide a mechanical interface to the PCB
- Help transfer heat from the circuit/die to the PCB and/or heatsink
- Provide a consistent interface for production testing
- Help facilitate circuit-function integration in a small area.
Selection of the package material is a key design factor for achieving a product's design objectives. Material selection considerations include CTE (coefficient of thermal expansion) mismatch, heat conduction, environmental conditions, and cost.
One of the package's purposes is to remove heat from the IC. Methods of heat dissipation include convection from natural or forced airflow, and/or direct conduction to the PCB via the package interconnects. Some packages incorporate metal bases on the mounting surface to facilitate additional heat conduction.
Plastic, ceramic, and metal are the most common materials used in packaging. Molded plastic packages are widely used for wireless frequencies under 6 GHz. They are inexpensive and compatible with most standard board-manufacturing processes. The disadvantage of plastic packaging is its poor heat conductivity, limiting its use to applications where the total package power dissipation is typically below 1 watt.
Ceramic packaging offers better heat conductivity than plastic, and can extend the total package power dissipation to about 5 watts. Ceramic also offers improved electrical performance, and has the ability to be hermetically sealed. However, ceramic packaging is relatively expensive compared to plastic.
Metal packaging offers the best thermal conductivity, extending the total package power dissipation to 30 watts. Metal also offers hermetic-sealing advantages. The big disadvantage of metal packaging is its high manufacturing cost.
Packages Come in Many Styles
A wide variety of packages are used for commercial wireless products—they can be divided into two broad categories: leaded IC packages and leadless IC packages. Leaded packages are inexpensive and widely used, offering low-to-moderate electrical performance for wireless IC applications. However, most leaded packages have significant parasitic effects, limiting their performance in many applications.
Although a variety of leaded packages are available for wireless applications, relatively few leaded package "standards" exist. Even industry workhorses such as the SOIC package have enough physical differences between manufacturers that modeling package performance can be a custom effort. The only certainty is that these packages have the same pitch and share a common lead pattern.
The familiar dual-inline packages (DIPs) are large, and therefore have a low pin-count per given area, reducing the integration level of the enclosed chips. Also, the bulkiness and inductance of the package leads make DIP packaging impractical for handling high-frequency wireless IC applications.
PGAs (pin-grid arrays), PLCCs, and QFPs are leaded package types that have previously been used for CPUs and high-speed logic, but have limited use in high-frequency wireless applications due to physical parasitic effects.
SOIC and SSOP packages have gained a foothold in cellular and PCS applications due to their low cost and adaptability to standard surface-mount manufacturing processes. Figure 1 illustrates an SOIC 8 package used for wireless ICs, typical of the type of package used in a number of RFIC applications. Because of the finer lead pitch, the SOIC's overall packaging density is higher than a DIP's, and the smaller lead inductance gives the SOIC package acceptable signal-handling characteristics up to about 4 GHz.
Figure 1: The SOIC 8 package is often used in RFIC applications below 4 GHz |
Strip-lead packages for RF and microwave use have been in the industry in one form or another for quite a while. They are characterized by a discontinuous metal frame along the package mounting surface, with launches into strip-lead packages that are either microstrip or coplanar. Their construction results in large signal-path inductance, and a corresponding limited frequency response.
Multi-chip modules (MCMs) are becoming popular in the wireless arena because they can handle the integration of many circuit functions in a small area and are relatively cost-effective. An MCM typically utilizes several ICs, each with a specific function, to achieve a high degree of integration. The short length of signal line between chips in the package can result in improved signal integrity between chip functions. The cost effectiveness stems from the reduced number of packages needed to integrate the required functions, along with savings in PCB real estate.
Leadless IC Packages
Leadless IC packages are quickly becoming popular. These packages are relatively low in cost and offer a tremendous size and performance advantage over leaded parts. This advantage translates into higher integration per unit area, and the ability to handle applications where speed is of paramount importance. Therefore, the leadless package is the foundation for the high-frequency package solution.
With the performance advantage of leadless packages, devices that operate above 6 GHz can now be assembled using standard high-volume manufacturing processes and integrated onto the same PCB as the IF and modem circuits. This results in much lower packaging cost, higher reliability, and higher levels of integration.
Leadless packages, however, have constraints on their use that designers must take into account. Most leadless packages are constructed of ceramics, either high-temperature fired ceramics such as alumina, or low-temperature co-fired ceramic (LTCC). Because of the relatively high thermal resistance of this material, true SMT leadless ceramic packages have a moderate limitation on total-package power dissipation. When used for power amplifiers, typical packages only support 1/2 to 1-watt PA performance without the use of integrated heat spreaders. Another disadvantage of ceramic packages is their low CTE, which typically does not match the CTE of today's popular PCB materials. When larger ceramic packages are mounted onto PCBs and subjected to wide temperature extremes, large stresses can build up in the package, causing fracturing of the attachment joints or in the package itself.
Drop-in packages are capable of extending the frequency response of circuits to beyond 18 GHz, but are relatively expensive due to their complicated manufacturing processes. Another disadvantage is the absence of a well-defined thermal path. All heat generated in the package must be dispersed either through the air or by conduction through the ceramic. Flip-chip packages also extend frequency response; thus they improve integration density even further. With these packages, the die is mounted on an interface material that is then attached to the PCB via solder balls. The disadvantages of flip-chip processing are degraded thermal performance and more complex assembly methods.
Several SMT packages are compatible with standard manufacturing processes and pick-and-place machines. Some manufacturers use LTCC processing, allowing for the buildup of grounded sidewalls. SMT packaging benefits from reduced package height and, therefore, offers the promise of improved performance beyond 40 GHz. The disadvantage of this package is that it can experience increased mechanical stress due to CTE mismatches with the PCB, causing failure of the package or attachment joint. To mitigate this risk and provide superior high-frequency performance, true SMT packages are sometimes restricted in size, reducing mechanical strain on the package edges caused by CTE mismatch.
Chip-on-Board (COB) technology combines the package with the PCB or substrate material, with the die directly mounted on the substrate, connected with bond wires or solders balls. An encapsulating material is then deposited on top of the die, acting as the package body and protecting the die. COB technology has lower manufacturing costs but requires the use of specialized equipment and processes.
The Ball-Grid Array
One of the most promising technologies, combining high performance, low cost, and reliability, is the Ball-Grid Array (BGA) package. Originally a solution for high-speed, high-pin-density digital ICs, BGA packaging has made its way into the high-frequency marketplace. BGAs are stretching the performance barriers to 30 GHz and beyond, and are facilitating the expansion of high-speed communications both for wireless and wireline applications. Construction of the standard BGA package is relatively simple (Figure 2).
Figure 2: The basic construction of a BGA package |
Several conclusions can be drawn from an examination of the available packaging options:
- Several packaging options are available to the wireless IC designer.
- Few of the "standard" packages can be accurately modeled, due to the manufacturing differences among suppliers.
- Leaded packages inherently have large parasitic effects and do not offer a high-performance, low-cost solution to broadband wireless designers working at higher microwave frequencies.
- Heat management is a major issue in many applications, and the proper selection of packaging materials and mounting is essential to prevent thermal problems from disrupting reliable operation.
- Mechanical stress, either externally applied or induced from CTE mismatch, is a major reliability concern when designing a package.
Improving the Package Design Flow
An IC designer rarely has packaging models available when developing a wireless IC and the packaging is often designed by electromechanical engineers, away from the main IC design flow. As a result, these different design activities must be "married" near the end of the IC design process—the engineers must rely on blind faith that the package design will work with the IC design. Only bench measurements can validate this faith.
At the end of the initial IC design process, if the engineers determine that the package parasitic effects degrade the product performance significantly, the product must be externally compensated, redesigned, or accepted as-is with reduced performance. In any event, the outcome is a slip in schedule and an increase in product-development costs.
However, the design process can be improved. While it is essential that mechanical and thermal analysis be done on a package application, it is also valuable to have valid electrical package models available to the IC designer at the start of the design process. With this data available from the start, unpleasant surprises are prevented, reducing time to market and lowering development costs. There are several design methodologies that can improve the process.
The first method involves designing the wireless IC concurrently with the package, and co-simulating the package model using the IC circuit model. This composite model can be used to improve the IC and/or package combination to achieve optimum performance. Analysis tools capable of both circuit and electromagnetic (EM) simulation allow integration of packaging within the normal wireless IC flow.
A second, and better, method to improve the design flow is to create a series of standard package models to use during the wireless-communications IC design process. In this way, the package model is available at the onset of the design process, for use by the IC designer in an integrated design environment. In either case, faster time to market and lower product-development cost are achieved over the typical disconnected design flows that exist today.
There are a great variety of package types available, some suitable for wireless applications and some not. It is important to select the proper package type to ensure that your design can be manufactured efficiently and operate reliably. You must keep in mind that even standardized packages require modeling or characterization to allow for differences in the physical manufacturing implementation of the package.
Managing Package/IC Design with Integrated Design Tools
In addition to the typical mechanical and thermal analysis of a package for RFIC applications, it is also important to have valid electrical models for the package at the start of the design process. Concurrent design of the wireless-IC application and its package means the package model can be co-simulated using the IC circuit model. You can use this composite model to combine the IC and/or package design to achieve optimum performance.
Figure 3: Example design tool for integrating an IC package within the IC design flow (Agilent's Momentum 2.5D EM simulator in Advanced Design System) |
An EM modeling simulator that is part of the integrated IC design environment lets you analyze a new class of problems previously off-limits to EM tools. You can optimize the physical characteristics of the model to obtain the specified performance within predefined limits, saving considerable time in the design process.
To learn more about ADS, Momentum, and links to Agilent test equipment, visit www.agilent.com/find/eesof.
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About the Author
Chris M. Mueth currently works as the Product Marketing Manager for Communications Systems Design and Verification products at Agilent Technologies EEsof. He received his electrical engineering degree from California State University, Northridge, and his MBA from Pepperdine University. Chris has worked in product development at various levels for the past two decades, specializing in the development of electronic components and subsystems for communications applications.
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