Mobile entertainment is a major driver for the next-generation wireless market. In fact, one noted wireless semiconductor leader is extending the functionality of mobile handsets to include a broad range of media applications. Customers rely heavily on the company for early access to working prototypes and system software. This enables them to get a jump start on developing their own systems on chip (SoCs) and embedded application software, and to bring new products to market ahead of silicon and ahead of their competition.

To meet the pressures of this highly competitive marketplace, the company had to adopt new approaches to shrink its product development cycle. The most important was parallelizing its hardware and software development flows. It needed early prototypes of next-generation processors for its system software development teams so it could begin development of OS enhancements and drivers ahead of actual silicon. For this task, it selected a hardware emulation solution from Emulation and Verification Engineering (EVE).

Like most developers of complex integrated circuits (ICs), its engineers use simulation to verify their SoCs at the register transfer level (RTL) and then perform integration-level test cases at the full chip level. However, with chip designs in excess of 10 million logic gates, chip-level simulation performance is less than one cycle per second, inadequate for booting the OS or running actual application software. Consequently, once the basic functionality of the chip has been verified in simulation, the design is moved into a hardware prototype where run-time performance of several MHz is achieved.

In the design flow, it initially used an entry-level emulation system with 1.5 million gate capacity to model an ARM processor or digital signal processor (DSP) core and selected elements around it. The emulation system is used by the chip design team for processor verification, and by the software development team for validating low-level system software. Once RTL code for the rest of the chip is available, the entire design is moved to a higher-capacity, higher-performance emulation system, which has a maximum capacity of 50 million gates for full system-level verification. This system-level prototype is then deployed to all the software development groups for local application development and validation. For this purpose, it uses a "replicate" configuration of the emulation system optimized for embedded software development at a lower cost than a full emulation system.

Figure 1:  The front end of each transactor that communicates at a high-level of abstraction with each peripheral is modeled in C on the PC

This new emulation system offers several benefits over traditional prototypes. For one, the entire design is contained within its hardware and its associated PC, which means no target board is required, nor external cabling, level shifters or speed-bridges. Instead, the company built a series of transactor models for each aspect of the user interface, including keypad, LCD display and camera sensor. The front end of each transactor that communicates at a high-level of abstraction with each peripheral is modeled in C on the PC (Figure 1). The back end that converts high-level commands into bit-level protocols is mapped to hardware within the emulation system's Reconfigurable Test Bench (RTB) architecture (Figure 2).

Figure 2:  The back end that converts high-level commands into bit-level protocols is mapped to hardware within the emulation system's RTB architecture

The SoC itself is modeled entirely in the emulation system's field programmable gate arrays (FPGA) resources. Its RTB architecture ensures that communication between transactors and hardware is efficient for optimum run-time performance. As a result, the emulation system operates at megahertz speed, while exhibiting behavior that is true to the final silicon.

In addition to making the prototype inherently more reliable, the emulation system's self-contained environment does not require human intervention for connecting/disconnecting external peripherals. The obvious benefit is that hardware and software development teams worldwide can share a single system at different times during the day for different designs. For example, the SoC design team in France uses it during the day for hardware verification and, when they leave for the evening, the team in Japan can download a different design and use the same system for software development. In this way, the emulation system is kept running 24x7 with no local attendant required.

Previously, the design team used a traditional FPGA prototyping system and typically spent weeks trying to get their design to work correctly in the system. Such things as multi-FPGA partitioning, clock distribution, memory mapping, bus handling required manual intervention. When the inevitable design change would occur, they often had to start the entire mapping process from scratch and incur several more weeks of effort to get the modified design working correctly on the FPGA hardware. Once the prototype was working correctly, the next hurdle was debugging. Internal visibility was limited or non-existent and changing test points required major rework. As a result of these issues, it took a team of 12 engineers to support a single prototyping project.

Switching to an emulation-based methodology, the company was able to bring up the design on the emulator in just a few days, and typical design changes could be accommodated in less than a day. In addition, it could quickly debug problems with the emulation system's interactive debugging environment. It attributes this difference to the emulation system's software, which automates the entire mapping process, and to its RTB architecture, which provides full read/write design register and design memory access for efficient debugging.

In the past, the goal was to deliver a stripped-down prototype system to software developers, and even then projects were often a month late. Now, the company is delivering complete emulation systems ahead of schedule. The real benefit, however, is that it's now able to ship higher quality engineering samples to customers, with a complete, validated software infrastructure. It's hard to measure the financial impact of helping customers bring products to market sooner, but the difference is huge.