San Francisco - ParthusCeva Inc. is adding models of phase-locked loops for the 0.13-micron process of foundry Taiwan Semiconductor Manufacturing Co. to PLLXpert, its Web site of PLL design information and intellectual-property (IP) cores.
A compiler at the site, www.pllxpert.com, will construct a PLL in response to specific user inputs. The system effectively allows designers to roll their own PLL cores using a configurable platform that has been tested with various designs and processes, said Kieran Flynn, PLL business manager for ParthusCeva (San Jose, Calif.).
"Think about the hundreds of designers out there in fabless semi companies who need one or two PLLs a year," Flynn said. "A PLL is full of trade-offs: frequency vs. power consumption, area vs. noise immunity. But at the end of the day 90 percent of PLL users just want a good, stable device that locks at their desired clock frequency and offers some flexibility in case they need to change those clocks for some reason. They are more than willing to compromise some of the degrees of freedom in return for minimizing risk."
What such designers want, Flynn said, "is a data sheet, proof it works and fast delivery." The PLLXpert environment effectively offers an interactive data sheet and a "pay when you use" business model, he said.
ParthusCeva was formed by the merger of Parthus Technologies plc (Dublin, Ireland), an analog IP provider, and the Ceva division of DSP Group (Herzelia, Israel). PLLXpert was set up last year to help the company distribute mixed-signal IP.
Barcelona's version
The online service is in many respects similar to the one offered by Barcelona Design Inc. (Newark, Calif.). Barcelona says its tools allow designers to construct op amps and PLLs by inputting critical parameters and specifications into an online system that uses synthesizable IP blocks. The IP choices are bound by process "engines" provided by the major silicon foundries, so the design process frequently involves little more than a modification to an existing TSMC macromodel rather than a design constructed from scratch.
ParthusCeva's compiler allows designers to harness an existing architecture by creating a PLL that is centered to their input and output clock requirements. The design engine provides access to several kinds of PLLs. Some are characterized according to the specific applications they support, such as double-data-rate memory, AGP graphics, PCI bus-to-USB 2.0 conversion, MPEG and digital.
Available PLL cores are also characterized by foundry processes, including the 0.25-, 0.18- and 0.13-micron processes of TSMC, United Microelectronics and Silterra Malaysia. PLL designs for each process are validated by a compiler calibration chip. A number of 90-nanometer PLL cores are also available, the company said.
