Wayne, N.J. - Network-processing units are finally getting a break, thanks to an improved market that is allowing communications industry chip suppliers to follow through on plans to offload dedicated functions to standalone chips. The shift is happening on two fronts, both of which should ease the strain on NPUs while providing speedier, more precise performance.
Layer 7 functions like Web switching, intrusion detection and XML processing are being moved off-chip, said Linley Gwennap, principal analyst at The Linley Group. Classification tasks on the ingress of a network processor are also being bumped over to other chips, reflecting design ideas that were formulated before the market nose-dived.
A clear trend toward increasing the lookups on a packet from two or three to as many as 10 lookups has opened the door for off-the-shelf classification capabilities that will decrease NPU overhead, said Gwennap, who is chairman of this week's Network Processors Conference West, which begins Tuesday in San Jose, Calif.
Three chip vendors-Bay Microsystems, Agere Systems and Cypress Semiconductor-are capitalizing on these market shifts by releasing chips at NPU West that they say will reduce the processing strain on NPUs.
Bay Microsystems Inc. (Santa Clara, Calif.) said it plans to unveil an ingress classification coprocessor that will tackle the increased lookups of today's networking designs. Developed around a superscalar pipelined architecture, Bay's Biscayne classification chip can conduct up to 14 recursive searches per packet at 10-Gbit/second line rates and deliver better than 400 million searches per second with programmable key generation. The chip delivers a programmable rule set that supports IPv4, IPv6, multiprotocol label switching (MPLS) and Layer 2/Layer 3 virtual private networking.
Bay Microsystems has also added multiple algorithms to the chip that can police differentiated services, MPLS, frame relay and ATM streams. "This is where policing should be done," said Bay president and chief executive officer Chuck Gershman.
A direct-map SRAM interface is also offered, for linking to ternary content-addressable memory (TCAM) products in order to perform table lookups.
Biscayne will be delivered in a 100-MHz version optimized for OC-48 designs and a 166-MHz version optimized for OC-192 applications. They will dissipate 3 and 5 watts, respectively, Bay said.
While Bay focuses on offloading ingress classification tasks, Agere Systems Inc. (Allentown, Pa.) said it will deliver a coprocessor that offloads the processing of AAL2 voice channels from its APP550 and APP530 NPUs. The APP100 coprocessor is an OC-12 part that delivers a 622-Mbit/s interface to the network processor and can support between 250 and 32,000 voice channels. Channel counts can increase with the addition of external SRAM. A 64-Mbit SRAM bolted on to the APP100 allows designers to hit the 32,000-channel mark, said Altaf Hussain, product-marketing manager at Agere.
The APP100 provides a glueless interface to the APP550 and APP530 processors through a POS-PHY interface. The 32-bit-wide interface can be configured for 8, 16 or 32 Mbits, allowing designers to adjust the interface for their design, Hussain said.
Analyst Gwennap said he isn't sold on the market's need for a dedicated AAL2 voice-processing chip. "We haven't seen a lot of people offloading voice capabilities," he said. Since NPUs can handle AAL2 processing in software, Gwennap questioned the value of adding another chip to the system design.
While agreeing that AAL2 voice processing can be done in software, Hussain said that these solutions cannot achieve the consistent number of voice channels provided by a standalone chip. As advanced Internet Protocol routing and other capabilities are dropped on the NPU, the number of AAL2 channels is decreasing. "Customers want a more scalable and predictable solution," Hussain said.
Improving the search
For its part, Cypress Semiconductor Corp. (San Jose) is looking to reduce the search overhead in NPUs with its Ayama 20000 TCAM-based network search engine IC.
Like the Ayama 10000 Cypress launched in June, the Ayama 20000 can achieve 266 million searches/s and is available in 9- and 18-Mbit densities. The chip delivers the block-based routing, soft priority-table management and multisearch capabilities of the 10000 devices, features that ease an NPU's search chores.
To increase access time and thus reduce processor cycles even further, however, Cypress has embedded two LA-1 interfaces, thus giving processors two interfaces into the search engine. At the same time, the company has made changes at LA-1's logical layer so that designers can reuse portions of the key in subsequent searches, thus speeding search times, said product-marketing manager Gangesh Ganesan.
In addition, Cypress has added an atomic communication sequence that allows an NPU to perform a whole set of searches. "You write all the searches at once to Ayama and get back a block of results," Ganesan said. "The NPU then doesn't have to perform one search at a time, thus reducing cycle count."
To complement this capability, Cypress is delivering an associative data manager that lets a system search a TCAM database and execute from a separate SRAM in a single step. The Ayama 20000 also pulls in the assist table typically embedded on NPUs.
Bay's Biscayne chip and Cypress' Ayama 20000 will sample in the first quarter of 2004, while Agere's APP100 is to begin sampling in November. Cypress will also launch at NPC West an algorithmic-based network search engine, that Sahasra 50000, optimized for storing forwarding tables.
