MANHASSET, N.Y. — Adamant that the drive to third-generation cellular has more to do with increasing voice capacity than with high-speed data, Morphics Technology Inc. has released architectural details of a highly parallel baseband processor that the capacity problem, the company said.
Eschewing the standard DSP-plus-ASIC approach to wireless basestation design, the 3G Baseband Processor 64 uses a multithreaded architecture that separates the control and data planes to make the complex Layer 1 and high-speed data processing completely independent. An object-oriented, hardware-independent virtual-machine interface programming model links the two to provide for rapid development while also maintaining the developer's investment in the Layer 1 control software.
"Current designs are expensive and are limited by their single-threaded architecture," said Paul Ekas, director of product marketing at Morphics. "We've designed the processor from the ground up with multiple parallel data flows to get the performance needed for 3G, wideband-CDMA processing."
In addition, Ekas said, "those same, established architectures are limited to evolutionary growth, as they have to keep software backward compatibility to maintain their investment. We're not limited in that way, since our software is completely hardware independent. It automatically detects the configuration [that is, the number of data flow paths] and configures itself accordingly."
Sampling now to key customers, the processor is built in a 0.18-micron process and delivers more than 500 billion operations per second at 200 MHz, said Marc Ostrowski, also a director of product marketing at Morphics. The device consumes 6 watts and can process up to 64 channels at a time, he said. The company plans to introduce a 128-channel version next year, said Ekas.
The baseband processor supports up to 12 uplink antennas and 24 downlink antennas.
The company does not plan to make a formal product announcement before September.
