While the Virtex-II Pro family from Xilinx Inc. may represent only an expansion of an existing FPGA architecture in some embedded applications, the addition of PowerPC processors and multigigabit serial transceivers speaks volumes to communication applications. Xilinx is expecting Virtex-II Pro to chip away at ASIC business in edge routers and switches, even as it seeps into the market for standard network processors.
Along with IBM's PowerPC 405 architecture, Xilinx also licensed IBM's nine-metal-layer copper interconnect process and Mindspeed Technologies' Skyrail serial I/O architecture-dubbing it Rocket I/O-for use in FPGAs.
A new concept for hard intellectual-property core placement, originally launched with the Virtex-II family in 1998, makes it possible to "immerse" a hard block of logic in the Xilinx tile-based topology, giving designers the flexibility to place PowerPC blocks in many locations on a die. This increases efficiency to the point where a PowerPC core occupies only a few percentage points of total die area, Xilinx said.
Erich Goetting, vice president and general manager of advanced products, said the immersion concept met a key objective of "viewing the entire FPGA as a checkerboard, where tiles could be removed and hard cores placed at will, achieving the equivalent of ASIC technology for hard-IP insertion."
Among several members of the Pro family are a low-end device with no PowerPC blocks but four Rocket I/O pads for simple multigigabit transceiver functions. At the high end, the XC2VP50 FPGA has four 300-MHz PowerPC cores and 16 Rocket I/O blocks.
Kent Dahlgren, market consultant for communication applications, said that the PowerPC allowed the use of on-chip memory controllers, easing the implementation of lookup-table memories and simplifying interrupts. An internal CoreConnect bus supports a 64-bit bus to link the PowerPC to peripheral cores.
With Xilinx's implementation of higher-layer metal routing, only those routes that need to interface to the PowerPC cores do so, allowing other data paths to bypass the cores.
"The flexibility of buses makes the cores optimal for either control plane or data path tasks," Dahlgren said.
The serial transceiver blocks provide up to 3.125 Gbits/second per block. Blocks are programmable at both the data link layers and directly at the physical layers, allowing changes in functions such as speed, encoding, scrambling and cyclic redundancy checks. This way, the I/O blocks can be programmed on the fly for any of myriad high-speed interfaces.
Support for several voltage interface levels, including the LVDS interfaces used in parallel applications, can be implemented in the blocks. Serial and parallel interfaces can be used in the same FPGA, or all-serial solutions with aggregate bandwidth up to 50 Gbits/s.
Development environments come from Wind River Systems and GNU, and Xilnix is updating its own ISE EDA environment with SmartModels for PowerPC and Rocket I/O.
Volume prices range from $120 for the single-processor XC2VP4 to $525 for the dual-processor, eight-I/O XC2VP20. Goetting said he does not see the Pro subsuming the standard Virtex-II, as many customers will mix FPGA types, even within a single system.
Xilinx; www.xilinx.com.
