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24 July 2008
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Sidebar
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Internet Appliance Chip Design
SOC components are critical
to the cost reduction, size reduction, and performance enhancement of information appliances. SOC design is not simply IC design. It is systems design encompassing hardware and software development, with the added difficulty that there is no wire-wrap version of an SOC with which to develop application and system software.
The primary SOC hardware design challenges are functional block integration, chip design verification, manufacturing test and hardware/software coverification. The integration
platform is one element in an approach to these challenges.
An integration platform targeted at communications SOC design is shown in
Figure 1
. In this particular case, the control and signal processing are executed by the ARM processor and the DSP Groupýs OAK DSP. Other functional blocks are equipped with interfaces to the AMBA 2.0 and OAK data buses, enabling fast integration and multiple re-use. The dual-port mail box (DPMB) allows asynchronous communication
between the microprocessor and DSP. The use of multiple DPMBs enables the use of multiple processors on one SOC, a growing necessity for communication-enabled media devices.
Internet telephony and MP3 audio
This 10 million-transistor SOC was designed to significantly reduce the cost of the customer's original board-level Internet (voice over IP) phone. It
is a single chip that runs voice compression, modem, TCP/IP stack, and applications software.
The chip is capable of both fast 32-bit bus operation in a 240-pin package and slower 16-bit bus operation in a 160-pin package. The 32-bit option can access four times as much memory and has more parallel I/O, one more UART, and more chip selects than the 16-bit option. Thus, it is thus ýfuture proofedý for a wide range of user interface and communication options.
To meet the single-chip
requirement, the system was migrated from proprietary discrete processors to third-party embedded processors supported by multiple semiconductor manufacturers. The processors are the ARM7TDMI 32-bit RISC operating at 24 MHz, and two OAK 16-bit DSPs operating at up to 40 MIPS. The original hardware-only 33.6-kbps V.34 modem was replaced by a software/DSP modem. The G.723.1 and G.729 codecs, the echo cancellation, and tone detection were all implemented in an OAK DSP. The codec software was purchased off-the-shelf.
Applications and pSOS-based system software were developed prior to SOC availability, using a functionally approximate emulation board consisting of the processor, memory, and peripheral combination. Software porting to the SOC was executed later with minor modifications.
Verification
The usual functional, physical layout, and timing verifications were
executed with design tools. In addition, the design required a complex chip test strategy, hardware/software coverification, and confirmation of the chip's ability to interface with external communication components.
The chip test utilized the usual combination of functional and parametric tests. Additionally, the observability problem in testing and debugging three deeply-embedded processors was solved by multiplexing critical processor nodes to external pins. The 160-pin version contains only 108
non-power/ground pins, so a non-trivial multiplex scheme was deployed to allow three functional pins to be used as test pins thereby enabling any one of seven test modes. Random logic was tested using a combination of functional vectors, and ATPG vectors applied using eighteen scan chains of equal length. The chip deploys IEEE 1149.1 with an additional pin for reset, which is important in debug.
Hardware/software coverification was initially accomplished using the emulation board, and subsequently with
the chip itself. The customer's desire to sell the chip to other Internet phone manufacturers requires it to interface with various codecs. In-circuit emulation is a reliable methodology when verifying operation with external black-box components. Thus, the chip's hardware description language (HDL) description was implemented in an FPGA that was connected between an OAK development board and each of the target codecs. A verification suite was developed to confirm interoperability.
The final path
An integration platform approach speeds integration and verification of complex integrated circuits, including multiple on-chip design-for-test approaches. A board-level approach is still required to ensure timely software development, hardware/software coverification and the hardware emulation necessary for the integrated circuit to be a true system-on-chip.
Acknowledgements
Anne Ambler, Cadence Livingston Design Center, Scotland.
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