Building Blocks
Give Thanks for Phase Locked Loops
One of the most versatile circuits in communications, the PLL is a
fundamental application of numerous theoretical design engineering principles. Here, the PLL is defined, and basic applications are discussed.
By Rob Howald
The last few columns have endeavored to introduce some of the major, more complicated topics in communications, including equalization, carrier synchronization, and spread spectrum. With the holidays approaching, "Building Blocks" will take a slight breather from topics closely tied to state-of-the-art development. This
month, we are backtracking over some previous ground to clean up an important sub-topic. Repeatedly throughout the year, phase locked loops (PLLs) have been discussed in the pages of this magazine in the context of a larger system problem. Indeed, it is hard to think of a more fundamental application of a multitude of important theoretical and design engineering principles than a PLL. This month's piece is written for every digit-head, networker, softwarrior, or ASIC animal who recognizes PLL in a block
diagram, knows its importance, and yearns desperately for a more informative discussion.
Now, if you want all the math and are also interested in high frequency PLL design, it's important to point out that hardly a month goes by without one of the trade publications aimed at RF types running something PLL-related. This is indicative of both the topic's importance and the wide-ranging functionality that such a basic, simple element can have. In addition, an outstanding feature on wireless applications of
PLLs appeared in Communication Systems Design in February, 1996, pages 34-44, entitled "PLL Utilization in Wireless Communications." This month's column will first discuss what a PLL is, then describe many of its basic applications.
The basic control loop
A phase locked loop is a control circuit designed to control the...phase! A PLL has four primary components, shown in Figure 1. They are a phase reference, typically a very high stability oscillator, such as a
crystal; a voltage controlled oscillator (VCO), a circuit which responds to input voltages by changing its output frequency; a comparison mechanism, or phase comparator, which generates an error signal representing the relative relationship of these signals; and a loop filter, which operates on the error signal before delivering it to the VCO to complete the negative feedback. The prescalar and dividers in Figure 1 are also very common in PLLs, but conceptually add little to PLL operation except absolute output
frequency. While the PLL emphasizes phase lock, it is important to note that this implicitly also means frequency lock, although this is not necessarily true of the reverse.
The PLL is a classic example of a feedback control loop from undergraduate Control Systems 101. Of course, I remember Controls 101 about as well as I remember semiconductor physics theory. Fortunately for me, the PLL represents one of maybe three items on the list of practical techniques I learned as an undergrad that I have had the
chance to apply in real life. The most common PLLs are fundamentally second-order structures, which can be implemented with several loop filter variations. The most common of these use a lead-lag loop filter network ý a fancy name for two resistors and a capacitor. Sometimes, it is implemented with an op amp, and sometimes just with the passive components. The second-order nature is very convenient, as is the lead-lag circuit, because it creates loop equations described in typical servo terms as natural
frequency and damping. This fundamental second-order response is low pass in nature, with transient response and associated ringing a function of natural frequency and damping. This low pass closed-loop function is equivalent to wrapping a very narrow bandpass filter around the RF carrier that is output from the VCO. Such a filter is much narrower than any discrete filter at RF that could be easily fabricated, and can filter close-in carrier noise under the designer's discretion.
Frequency generation
Communications over RF channels requires a means to get the carrier signal to RF and back. The means to do so are upconverters and downconverters. The two primary design exercises of frequency converters are synthesizer design, which consists primarily of oscillators (crystal and VCOs) and PLLs, and design of the RF chain, consisting mostly of mixers, amplifiers, and filters. The purpose of the synthesizer design is to generate the carrier frequency. Ignoring the details of
single conversion versus double (or more) conversion, the synthesizer based on a PLL is a powerful tool for generating a range of carrier frequencies with little effort. A single loop, direct-divide PLL synthesizer is shown in Figure 1.
In Figure 1, the PLL has an output frequency of (Fout) = (N/R)(Fin). Another important advantage is that this circuit is capable of generating a wide range of carrier frequencies by changing N and R. In today's synthesizer technology, these values are easily changed
digitally by writing a divider programming word into a register inside a synthesizer IC. There are constraints on N and R, but the range of frequencies available will generally be limited by the VCO pulling range, which will be on the order of one octave for a typical wideband RF VCO. Since many service applications span significantly less than this, it is generally the case that a single PLL circuit serves as the local oscillator (LO) generation mechanism for a frequency division multiple access (FDMA) product
over its complete operating band, simply by programming the divider properly. These capabilities have brought about simple, low-cost, synthesizer design with low power consumption ý ideal for the wireless market. These chips continue to evolve towards ridiculously low noise (someone please contact me and tell me how these are measured), lower power, higher input frequencies, and smaller packages. The issue of phase noise and digital communications is very involved. However, PLLs are a straightforward means
to generate high quality RF carriers suitable for quadrature amplitude modualtion (M-QAM) digital communications. Wireless systems are usually too entrenched in some offset quadrature phase shift keying (QPSK) mode, minimum shift keying (MSK), etc., to be power-amp friendly, and these schemes are very robust to phase noise.
Figure 1
Tuners
In the cable television (CATV) world, frequency synthesizer downconversion subsystems in
the home go by the name "tuners." The tuner selects one desired video signal from a complete set of analog video channels. Because of the various standardized frequency plans, programmable PLL frequency synthesis is ideal for allowing a single design to be implemented in multiple applications.
Unfortunately, the multiple plans force the PLLs to have a very low phase-comparison frequency because the output frequency in a direct divide synthesizer must be a multiple of this comparison frequency without
any special tricks.
For RF output frequencies with comparison frequencies in the low kHz range, the PLL implements a very large divide ratio, given by Ntotal = F(VCO)/F (compare). As previously described, the noise multiplication factor of the crystal increases with the divide ratio. This is also true of the logic noise of the ICs in the PLL, resulting in each being increased by 20Log(Ntotal). For analog video, such performance was suitable. However, today, mixed in amongst the analog video are digital
M-QAM signals, a type of signal specifically not well-suited to phase-noisy RF carriers. Thus, careful consideration of link phase noise impairments becomes critical to proper implementation of M-QAM, particularly when leveraging existing tuner hardware for that application. Incidentally, frequency generation via PLL synthesis in a CATV headend is implemented in much the same fashion.
Carrier and timing recovery
In the past, we've discussed how PLLs generate local
oscillator signals that are coherent with some high stability reference at a transmit station. The concept of coherence comes across repeatedly in digital modulation. Once again referencing a previous Communications Systems Design article (filed neatly away, right?), a two-part feature entitled "Modulation Basics for Digital Communications" from July, 1996, pages 34-43, and August, 1996, pages 32-38, coherent modulations are associated with data detection mechanisms that require a replication of the carrier at
the receiver in order to peel off the data stream. There is just one problem. The signal at the receiver is a modulated waveform, not a carrier. That problem was a main point of the previous piece, describing nonlinear methods by which a tone suitable for phase locking could be dragged out of a modulated waveform. In some special cases, an auxiliary pilot signal, essentially a separate continuous wave (CW) carrier specifically for phase referencing, may be available, but this is generally an inefficient use
of energy and spectrum.
Nonlinear techniques are straightforward and low cost. However, they also introduce loop SNR degradation, and M-QAM for M > 4 requires careful evaluation of the contributors to phase noise degradation. These noise problems are a primary reason that more complex decision directed approaches have evolved with popularity. Decision-directed loops and preamble sequences, containing known symbols to aid synchronization, are used for burst modems to quickly acquire a carrier phase for
demodulation of a data packet. Decision directed loops and Costas loops are really just more advanced versions of PLLs performing the same basic PLL functionality. A x4 plus PLL carrier recovery is shown in Figure 2.
Nonlinear techniques can also be used in timing recovery subsystems. The basic idea is the same, although the nonlinearity can vary much more in form. Methods such as absolute value, envelope detect, square law detect, and delay-and-multiply all result in discrete clock-related tones in the
frequency domain. The basic PLL is used in carrier and clock recovery in such a scheme by picking off this discrete tone with a filter, and using it as a reference signal input to a PLL. Also, in both the carrier and clock cases, digital receiver implementations often mean these tracking structures exist in an ASIC in the discrete domain, where the VCO is instead a numerically controlled oscillator (NCO), and the loop filter is in the discrete domain (z-transform domain). Phase detection even in most analog
PLLs is often digitally implemented. While the digital implementation has dynamics that differ in the discrete world, the basic operation of the control loop is the same.
Figure 2
Modulators
So we have learned that the PLL can create the carrier, and it can recover the carrier. As with the Ginsu knife collection, that's not all! It has been described how a PLL transfer function is a low-pass filter response. On an RF
carrier, it behaves like a narrow-band pass filter centered on the carrier. The transfer function essentially separates the output spectrum (the VCO output) into a composite of two sets of noise contributors: those that contribute inside the PLL bandwidth, and those that contribute outside the PLL bandwidth. Those within the bandwidth come primarily from the reference signal's noise characteristics and PLL logic noise, due to the IC and any prescalars.
Outside the bandwidth, the noise replicates that of the
VCO. In this fashion, we get the important high-frequency RF attributes of the VCO, but also the high stability attributes of the reference that it is being forced to follow. Thus, as a low pass filter, the PLL output tracks low-frequency reference components, but not high-frequency components. This knowledge leads to the ability of the PLL to perform modulation and demodulation. The PLL low-pass transfer function expresses the ratio of VCO output phase to reference input phase. By contrast, the transfer
function expressed by the ratio of phase detector output to reference input is high pass.
Recognizing the above transfer function properties, the VCO can be used as a phase or frequency modulator. This approach is generally best suited for analog modulation, but can also be applied to simple digital frequency shift keying (FSK) and bipolar phase shift keying (BPSK) schemes under the right conditions. The VCO control port varies the VCO frequency, so the VCO can be used as both the carrier generator and the
modulator in this fashion by summing the message into the VCO control port at the proper place. If the message is summed into the circuit in front of the PLL filter, the result is a VCO phase modulated by the message, provided that the message bandwidth is below the cutoff frequency of the low-pass PLL transfer function. If the message is inserted after the loop filter, then the transfer function to the VCO output is high pass. In this case, FM is generated, and the message bandwidth must not extend below
the PLL cutoff frequency. Thus, no frequency offset can be applied, because the rejection at dc is infinite. A VCO with a linear characteristic is required in this latter case, and highly suggested in the former. This is significant, because this type of characteristic requires a more complex and carefully designed oscillator circuit.
Demodulators
Used as a demodulator, the reference input to the PLL becomes the transmitted signal of whatever modulation is used (phase
modulation, PM, or frequency modulation, FM), scaled by the channel and corrupted by noise. PLLs can be used to coherently demodulate PM and FM. In fact, the PLL can also be used for coherent demodulation of AM. While incoherent means are typically associated with AM and FM, coherent single sideband (SSB) and vestigial sideband (VSB) can be used for highest-performance AM detection. Coherent FM improves the all-important FM threshold effect, whereby output signal-to-noise ratio (SNR) decreases much more
quickly than input (SNR) below a certain input SNR threshold.
Since the transfer function from reference input to phase detector output is high pass, PM on the modulated signal will appear at baseband at the output of the phase detector, if the modulation is above the loop bandwidth. The convenience of this is significant because the PLL recovers the message itself within a gain constant directly. The need for the PM modulation to be above the loop bandwidth is often inconvenient. It requires a higher
frequency range of PM than may be desired. This is why systems often encode such information on a subcarrier, modulated onto the main carrier. It is easy to get the subcarrier frequency above the loop bandwidth, and then strip it off at the phase detector output. The disadvantage, of course, is that now the information must be recovered from the subcarrier. However, at this point, the signal is successfully localized at the receiver, where there is more processing flexibility.
As the phase detector represents
the point at which phase information is recovered, the VCO represents the point at which frequency information can be recovered. As described, the control voltage of the VCO changes its output frequency, so this voltage closely represents the modulation on the VCO. Since a PLL tracks its reference out to its loop bandwidth, FM on the transmit signal serving as the reference will appear on the VCO output if it is within the bandwidth of the PLL transfer function. It will also be represented at baseband by
the voltage on the VCO control line.
Finally, it is important to recognize that the carrier tracking structures, such as the BPSK and QPSK, Costas loops, and decision feedback loops, represent PLLs acting as both carrier tracking mechanisms and digital demodulators, all in a single-circuit implementation.
Phase noise measurement
Manipulation of the PLL transfer function can also be used to provide a means for measuring the phase noise of a stable local oscillator.
Simplistically, the technique used is to implement an extremely low-noise and tunable synthesized source as a VCO, and use a device-under-test (DUT) as a reference for the PLL driving this VCO. This PLL is arranged to have an extremely narrow loop bandwidth, much lower than the desired offset frequency to be measured. Then, the output of the phase detector, which is high pass relative to the reference (the DUT), can be sent to an analyzer to measure the noise component. The narrow loop bandwidth assures
that the measurement is entirely the DUT noise from very close in, out to the maximum offset desired.
The super-duper looper
Driving home from a short vacation in Hersheypark, PA, my family snoozed comfortably while I suffered in that no-man's land of radio stations between areas of civilized humanity. I flicked off the static-ridden Dolly Parton song and decided to think through the topic for next month's Communications Systems Design column. You will be pleased to
know that my daughter of six chose this topic, as she awakened and immediately started in about the famous loop roller coaster at the park. She agreed with me, in exchange for a Starburst fruit chew, that the PLL is undoubtedly one of the most versatile circuits in communications. It has applications in both digital and analog modulation. It can modulate and demodulate; it can generate carriers; it can track them; it can even test their quality. And, in the most extreme case, pondering these possibilities, it
can save you from radio hell.
Robert Howald is a staff engineer in the transmission network systems group at Next Level Systems (formerly General Instrument's communications division) in Hatboro, PA. He has a BSEE and an MSEE from Villanova University, and is currently a PhD candidate at Drexel University.
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