High-Speed PHY Design
By Andy Turudic
Designers with experience in double-digit MHz design are finding themselves being asked to design positive-emitter coupled logic, or PECL circuits at 622 Mbps. Design techniques,
tools, and measurement equipment are nonexistent in the lab, yet a first-pass design success, critical to the deployment of equipment into an aggressive market window, is expected.
The Internet tsunami has brought forth peddlers of all sorts. Perhaps some of us would not profit from the explosive growth in the communication industry were it not for the socially less welcome forms of interaction that choke bandwidth and cause our JPEG files to take forever to download. Internet bandwidth demand has
instilled a tremendous (more than usual) degree of panic in marketing-types to deploy hardware into a medium that is seeing triple-digit annual subscriber growth. The lowest potential energy state of effluent flow ultimately settles on the designer where this panic manifests itself in shorter design cycles, a lack of test and measurement equipment and, ultimately, in trusting performance claims by suppliers of key strategic components in the physical (PHY) layer of network equipment.
Designers with experience in
double-digit MHz design are finding themselves being asked to design PECL circuits at 622 Mbps. Design techniques, tools, and measurement equipment are nonexistent in the lab, yet a first-pass design success, critical to the deployment of equipment into an aggressive market window, is expected. Designers in this right-sized industry find that they do not have the resources to implement a design with proper diligence and resort to pushing responsibility for certain aspects of their system performance down
to the component vendor. The same paradigm of Internet panic holds true with component vendors, where CEOs and marketing-types demand entry into an explosive marketplace for which their manufacturing process and design philosophies are not optimal. The pressure to sell results in strategies of distracting board and system designers by highlighting the secondary issues of low power, low voltage, and price, familiar to these purveyors due to their participation in noncommunication markets, and dancing around
the primary consideration of in-system communication performance and functionality.
Crosstalk
For digital designers, crosstalk used to be what the boss did when the designer was late in delivering a design. With the advent of communication links between systems that aggressively push the Shannon limits of the media, the “analogish” term of crosstalk has slowly begun to creep into digital systems designers’ vocabularies, causing most seasoned digital systems veterans to revise
design technique, including running SPICE simulation checks where possible. Crosstalk in digital systems typically manifests itself as time uncertainty, or jitter. The more affluent design shops procure test equipment, some costing six digits apiece, to characterize components, while the majority rely upon component vendors’ claims of performance and lab measurements.
Unfortunately, there are no component-level specifications, since all specifications for the network are at a systems level. Assurance
of meeting system-level performance requirements is typically obtained by choosing the highest specification margins in each of the PHY layer building blocks, regarding power supply rejection, jitter transfer, jitter tolerance, jitter generation, rise/fall time, eye opening, and eye symmetry as primary selection criteria. Secondary criteria of pricing, power supply voltages, and power dissipation are then considered after primary selection issues have been satisfied. This article will focus on some primary
criteria that have been observed as PHY layer problems, which while overlooked in component selection criteria, are characteristics that can severely compromise system-level performance and first-pass design success.
I’ll take a medium, please!
In digital logic courses, all digital signals had zero time uncertainty (jitter) and slew rates (rise/fall times) that would consume every joule of energy from the universe. Every designer has experienced pragmatic enlightenment at some point in his
or her career when an oscilloscope revealed time uncertainty as fuzziness in the time axis at the logic threshold and rise/fall times that, in some cases, caused waveforms to resemble sinewaves. No big deal, as long as the downstream logic knows a one from a zero. However, high performance communications introduces a new set of pitfalls to be considered. Media, be they backplane runs, twisted pair, coax, or fiber, introduces attenuation and delay that varies with frequency, length, and temperature. Any
active element in the path between the information source and the destination will further introduce its own form of impairment, primarily as time uncertainty when signals are regenerated. As distances increase, the data eye tends to close, both in amplitude and time, limiting the recoverability of data at a receiver.
Figure 1a
shows an impaired signal, as received after a length of coaxial cable, and the corresponding recovered data (
Figure 1b
) from a transceiver operating on 2.5-Gbps 8B-10B data. For a given medium and data rate, distance is the determining technical factor in a bake-off of pieces of communication equipment, and a maximally open eye at data launch is a requirement, not a luxury.
00101011 or 11010100?
All logic circuits must decide whether a signal is true or false. This decision level of truth is a voltage set by all-knowing committees, usually a weighted average value of the favorite level of those
participating. An example of a decision level for PECL is shown in
Figure 2a
. Note that the decision voltage is 3.7V in an ideal academic system, where greater voltages are true and less voltages are false. However, device offsets and turn-on/turn-off delays can vary this threshold somewhat. Further corruption of this decision voltage occurs, particularly in single-ended logic, when adjacent circuitry moves current around on resistive power buses, resulting in local drops in supply
voltage to which a switching threshold is referenced. As shown in
Figure 2b
, the real device threshold becomes fuzzy, which then translates to the time axis as uncertainty, or jitter.
One solution is to spend less time (faster rise time) through the threshold (
Figure 2c
), assuming that the power supplies are not further corrupted by single-ended switching noise. By utilizing a differential logic family or interface, noise from adjacent
circuitry is minimized, with the added benefits of common-mode supply noise rejection and symmetrical rise/fall times. These considerations are applicable to both intradevice as well as interdevice characteristics. A minimal-jitter Utopian design, both intercomponent and intracomponent, would then have the characteristics of high-supply noise rejection, low resistance and impedance power-supply connections, fast edge rates, precise edge placement, and symmetrical turn-on/turn-off characteristics. Minimum
jitter means greater eye opening, which means further distance in a given medium.
Being quiet when not listening
Integration is a desirable objective in any system — provided it is integration of functionality and not of system noise. There were early times when devices existed in pairs, one as transmit and one as receive, and the conjugation of these devices was the forbidden fruit of all PHY knowledge. As frequencies of communication systems increase, the less capable technologies will
fall back to that lower integration partitioning. With the Internet panic, this partitioning’s rationale appears to have been forgotten at 622 Mbps, and partitioning has given way to board space considerations and CEO aspirations. Vendors would display their new transceiver devices to prospective board designers with one unproclaimed caveat — the receiver was turned off during jitter measurements! A room temperature measurement of a transmitter circuit, performed with the receiver off, is shown in
Figure 3
. This does not appear to have been an intentionally misleading gesture, rather the jitter measurements were made on very specific test equipment optimized for measuring transmit jitter or receiver performance only. Even today, an integrated test system for simultaneous testing of transmit paths and receive paths is unknown to the author.
A more realistic measurement is to characterize a transceiver as it would be expected to perform in a worst-case scenario. Such
a problem became visible when a call was received from a designer who had unexplained, system-killing crosstalk in a network box that was ready to ship for field trials. Subsequent analysis, using an evaluation board from the suspect device vendor, showed nothing remarkable with the receiver off, though the device did fail jitter transfer measurements on the transmit synthesizer. Turning the receiver on at room temperature, with 8 high and 8 low nonreturn-to-zero (NRZ) bits, and with the frequency offset
to the synchronous optimal network (SONET) maximum of 20 parts per million (ppm), is shown in
Figure 4
. Performance was observed to decline at elevated temperatures. It is believed that poor substrate isolation may be the root cause of a significant portion of the observed jitter, since this vendor chose to use a semiconducting substrate. This seems to correlate to the degree of degradation observed in two vendors’ semi-insulating substrate devices measured and shown
in
Figures 5a
and
5b
. It is thought that the higher jitter device in
Figure 5a
is due to that vendor’s technology choices of single-ended logic and metallization resistance, which affects the degree of intercircuit supply-noise isolation. Output rise and fall times are easily compared between
Figures 4
and
5
, with slower rise times
resulting in higher jitter in the next device, typically a laser driver. All of these measurements are relative, requiring only a high-speed oscilloscope and frequency source.
Apples, tangerines, and valencias
Transceiver performance between vendors varies considerably, even when the candidate receiver is off and at room temperature, as shown in
Figures 4
and
5
, device b was sampling to the marketplace first and set a
standard to beat of 0.004 unit intervals (UI) of jitter, representing a 60% margin against an optical-system specification maximum of 0.01 UI root-mean-square (rms). For the uninitiated, a UI is one NRZ bit period (approximately 1.6075103 ns at 622.08 Mbps), the specifications are actually system-level measurements, and the measurements are made optically on single-mode fiber. Later devices from other vendors had claimed jitter generation that was within +50% of this value. Looking at jitter transfer, which is a
characteristic that defines the amplification of jitter in the frequency domain, only the device that was first introduced to the market was capable of meeting jitter generation and transfer specifications simultaneously.
By tuning an external loop-filter on the device that was first introduced to conform to the jitter-transfer bandwidth characteristics of the failing devices (approximately 2 MHz against a specification of 500 kHz), jitter generation was shown to be reduced by yet another factor of two
to about 0.002 UI. The jitter transfer characteristic is usually either not shown or is dismissed as being irrelevant by the newer vendors and is generally recognized by the component industry to be beyond the measurement capabilities of most small to medium sized development organizations.
Some optical transceiver module suppliers have capitalized on this fact by shipping noncompliant optomodules. Some vendors have chosen to label their devices as an “ATM transceiver,” recognizing their own
failure to meet public networking standards. With the current state of panic-mode hardware development, and with device costs being about equal, it is doubtful that any organization would condone the development of two identical speed and format network interfaces, where one is customer premises noncompliant and the other is public network compliant. System implications of oscillator cost are also affected by these performance criteria. Compliance typically carries little or no cost premium over noncompliance
in a transceiver and, from a system perspective, may actually reduce the high costs associated with precise-timing source oscillators.
Balancing the budget
Jitter from a system perspective, which is where the specifications lie, is a matter of shrewd technical budgeting. The system designer must draw a dotted line around all system components, including the oscillator, synthesizer phase-locked loop (PLL), multiplexer, PECL 50- driver, PECL 50- receiver, laser driver, laser, and receiver
circuits, to establish the trade-offs of cost, performance, and time-to-market. The issues discussed here affect all of these components to some degree, with even the often overlooked passive aspect of circuit layout being a contributing factor. Rather than waste precious resources measuring each combination of devices and layout, most successful system designers select each device with maximum specification margin or best performance, apply extreme care in circuit pack layout, and, at the first prototype,
pleasantly find themselves with a network standards compliant system. Now they’re building faster and bigger while their lagging competitors agonize over supply voltages, power, transmitters that don’t meet any specifications when the receiver is turned on, and poor rise times that create excessive laser driver jitter. Those competitors did meet their low power objectives, but nobody is plugging in their boxes.
Andy Turudic received a BASc from the University of Windsor in Canada in 1980. He
spent 11 years with Nortel and BNR designing various switching systems and widgets. He then spent close to 3 years at an RBOC, where he managed Bellcore and co-initiated OC192 system design and research in 1992 with Nim Cheung. Turudic joined TriQuint Semiconductor in late 1993 where he is a product architect. He can be reached at aturudic@tqs.com.
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