Building Blocks
Conversion is Key
Real strides in communications today are being made in two key areas — RF technologies and digital integration and
processing. Getting between the two requires some important elements, with data converters topping the list.
By Rob Howald
We will begin a semi-periodic “tour-de-digital” with an analog/ digital conversion discussion this month. It fits nicely with this time of year, given that the conversion itself is implanted in the month of June. We convert from spring to summer: We convert from children in school, to children in the parks, pools, and streets. Accompanying this is the conversion to
light, summer rush-hour traffic, without the big orange cones that always have the right-of-way. I personally convert from a sneezy, watery-eyed mess of May allergies to a freely breathing primate once again. My wife, who does 99.9% of the serious cooking, converts to a barbecue lobbyist (where she does about 50% of the serious cooking). Finally, the summer brings about a conversion to a slight workplace slow-down, due to golf, vacations, golf, after-hours activities, golf, etc. Because of this slowdown, I
eliminated the possibility of including any mathematical tedium in this column, knowing that many will surely be reading this on the beach, boat, or poolside. As a quick tip for packing before heading to sun and sand, the Building Blocks column in the May 1997 issue of
Communication Systems Design
titled “The Evolution of the Revolution” describes some interesting aspects of digital versus analog.
This column is to be the first of a three-part introduction to digital processing. In the
first two back-to-back pieces, we will concentrate on getting there and back. In other words, we will discuss analog-to-digital converters (ADCs) and digital-to-analog converters (DACs). Most of the discussion will be ADC-based, mainly because the thrust into digital has had such an impact on digital-communication receiver technology. A follow-up column to be published later this year will introduce concepts between the ADC and DAC. Two very important enabling technologies that have revolutionized modern
communication systems are DSP and VLSI (very large scale integration), which allows the miniaturization of the complex functionality used in digitally implemented subsystems.
The ADC and DAC topics are particularly enlightening. To truly understand them is a sign of a well-rounded engineer. In fact, they make great job interview topics, unless you are talking to someone for a job as a computer programmer (in which case you are making headway if they engage in intelligible conversation). The reasons that
ADC and DAC concepts are good indicators are obvious. First of all, there is the inherent need to be fluent in both analog and digital concepts. Also, there is a lot of important theory related to their operation, much of which is introduced at the undergraduate level (Nyquist Sampling). The high performance converters involve more advanced, interesting, and useful theory, as well as a skilled hardware designer to make them work optimally. The data rates involved nowadays require fluency in high-speed digital
techniques, RF concepts, and a whole lot of PCB design skill. Finally, if someone completely understands an ADC specification sheet, then either they designed the part themselves, or they work for Analog Devices, Burr-Brown, Linear Technology, or Harris. There are many intricate details associated with the specifications for ADC and DAC; keeping up-to-snuff on all of them is a sign of true diligence. This column will focus on some of the fundamental ideas.
Aliasing
The one idea almost
everyone has some familiarity with, even if the details are not understood, is aliasing. Successful sampling means taking samples of the analog waveform at a minimum of twice the frequency of the highest spectral component in the signal (discrete spectrum effects are conceptually easier to understand by thinking of an ADC, where there is a spectrum on the “A” side that is modified when converted into the “D” domain). While Nyquist is explained during those fuzzy undergrad years, this
description over-constrains the problem. It could be re-expressed using the concept of bandwidth instead of frequency component.
In
Figures 1
and
2
, the aliasing concept is graphically depicted. The baseband analog input spectrum is shown, along with the digitized version, for a properly sampled signal in Figure 1. In Figure 2, an undersampled version is shown. Note that here we are considering ideal sampling, meaning impulsive discrete samples
(as opposed to the necessary reality of rectangular pulses). Clearly, because of spectral overlap, the spectrum in Figure 2 does not provide a clear replication of the analog signal spectrum. There are applications where the signal processing is not meant to replicate the spectrum. Signal averaging or detection comes to mind most readily. Figure 1, by contrast, reveals a spectrum that maintains an undistorted version of the original spectrum, one that with proper filtering could be recreated exactly.
Mathematically speaking, the simplified Nyquist criteria requires the two-times sampling frequency. In practice, practical filtering constraints imply a need to sample more quickly, which spreads the repeated versions of the spectrum away from one another.
Note that aliasing works “both ways.” An out-of-band signal in the analog domain can interfere in the digital spectrum if it is above the Nyquist range and becomes aliased inband of the sampled desired version. For this reason, and the desire to
maintain a reasonable sampling rate, sharp “anti-alias” filters are often used before the ADC. In our simplified discussion, these would generally be low-pass filters. The danger here is that some of these filter topologies have regrowth in the stopband that must be carefully considered, and sharply attenuating responses tend to give the most grief in phase response (resulting in time domain dispersion).
Quantization and noise
The ADC provides a digitized version of the signal at its
input. The quantization process means expressing the signal in terms of a digital number. These are discrete step increments, in contrast to the continuum of values that an analog waveform can take on. The resolution of the converter, or the increments of voltage it can encode a sample of a waveform to, is related to the number of bits used to encode and the input range. A high performance ADC may have a ±1V input range (it isn’t nice to have to develop driver and load circuits to handle high
voltages at higher input frequencies). The number of ADC bits that a chip may have spans a wide range, but many applications settle on 8 bits, 10 bits, or 12 bits. The technology is constantly improving, to the point where 16 bits are available at once unforeseen possible sample rates. However, the situation remains that communication applications rarely require the kind of precision available with 16 bits, and other nonidealities will ruin the last few bits for you anyway.
If a most significant bit (MSB) is
half of full-scale, consider that the least significant bit (LSB) in an 8-bit ADC represents 2
-8
, or a signal variation -48 dB of full scale. Obviously, you won’t be seeing that on the oscilloscope, although it’s peanuts for a good spectrum analyzer. Each bit in the converter is worth 6 dB. (That little piece of information led an ill-advised submission to a technical journal I receive to claim that a -96-dB spurious performance in an all-digital frequency synthesizer was due to the use
of a 16-dB DAC.) Those kinds of numbers, in most cases, are a fantasy because of various other nonidealities and, in the vast majority of communication applications, they are also unnecessary. A designer must consider the need for having such waveform precision. Other processing functions and ADC implementation will likely cost the last few bits anyway. And those extra bits are very expensive.
Getting back to the “noise” part of the quantization, it is apparent from the digitization process that
the samples taken of the waveform will be assigned amplitude values that do not exactly match the analog version. The samples will fall between steps somewhere, and the error energy left over from this operation is called quantization noise. It is also clear that the quantization noise will be smaller as more bits of resolution are added, as will the step sizes within which the waveform falls. The step size is also related to the input voltage range. Because of this, the root mean square (rms) noise
expression involves both. The rms noise voltage is given by
[q/sqrt(12)
], where
q
is the voltage weight of the LSB (the voltage range divided by the number of discrete steps). A statistical characterization of this noise process is that it is uniformly distributed (see the Building Blocks in the April 1997
Communication Systems Design
, “In the Noise”). This means that, over the range
(-q/2)
to
(q/2),
the noise is as likely to take on any value in that range as it is
any other value. This is not strictly the case for a periodic signal, such as a sine wave, where noise processes also become periodic. Unfortunately, the sinusoid is still the typical full-scale waveform used as a reference in determining the ADC signal-to-quantization-noise (SQNR) ratio. So, on one hand we represent SQNR using a full-scale sinewave input reference, but, in fact, the quantization noise type used in the calculation does not precisely describe the scenario. However, in communications a
sinusoid is not a probable practical representation of the actual input anyway, and the noise associated with a more random waveform will be more likely to approximate the uniform case.
Another item of some note about the noise process is that the uniform probability density function (PDF) is not one seen often in communications — except here. The value of the variance is known from this PDF and allows a simple expression for an ADC’s SQNR.
SQNR
Continuing to be equation-free can no
longer be achieved. Sorry. (At least I didn’t say, “Read my lips — no new equations.”) Here it is, the basic, well-documented expression for SQNR assuming a full-scale sinusoidal input:
SQNR (dB) = 6.02 N + 10 log [ f
(sample)
/ 2f
(bandwidth)
] + 1.76 dB
Here is what it all means:
N = number of ADC bits
, which is why you may often hear the “6 dB per bit” mantra. The 1.76
dB is 10 log (3/2). The factor shows up when you do the variance calculation of the uniform PDF over the LSB range described (the term
N
is also from this). Finally, the middle term has to do with what the sample rate does to SQNR and emphasizes the benefits of oversampling. Finally, it is quite important to note that this is based on a full-scale input. This is important because the ADC implementations are of prime interest as gateways to a digital receiver or processor. At the receiver end of most
communication systems, there will be level variation that must be compatible with the ADC input dynamic range, and there are unsavory effects of being either too low or too high relative to full scale. In fact, in this sense, it mirrors many simple analog amplifiers in performance issues — the proper level is a trade-off of noise and distortion performance.
However, in an ADC or DAC, there are more obscure forms of distortion than in typical analog parts. The SQNR and these other distortions jointly
determine just how much bit resolution is really available, defined in specifications as effective number of bits (ENOB). In other words, a 10-bit ADC may only provide 9.3 bits of performance, due to internal noise and the distortions it generates.
One cautionary note: video folks measure signal-to-noise ratio (SNR) differently, using peak voltages, since video modulation is completely “downward.” This impacts how a paper discussing digitized video would express the SQNR.
Oversampling
We have discussed how sampling at the Nyquist rate is a theoretical necessity, and sampling at something reasonably higher than that allows room for practical filtering to be used. Another advantage of sampling higher, even much higher, is that the SQNR within the desired (i.e. original analog) bandwidth can be improved. The concept is illustrated in
Figure 3
and is very simple to comprehend. Basically, the quantization noise, as described, is fixed by input range and
the number of discrete steps (number of bits) in the conversion process. This number is independent of bandwidth. It is spread evenly over the Nyquist bandwidth. If the Nyquist bandwidth is wider due to the higher sample rate, the noise density is lowered to maintain the same total power in the spectrum. Thus, within the desired signal bandwidth, the SQNR improves, since the signal remains constant. The relationship is directly related to the fractional bandwidth above Nyquist used, where this out-of-band
noise “graveyard” means some of it can be filtered, with improvement resulting as described by the SQNR equation given earlier.
As always, there cannot be an arbitrary lowering of the noise floor forever. Eventually, the noise process will be dominated by items such as the noise floor of the ADC’s analog stages prior to quantization. In fact, even when not doing a lot of oversampling, it is a good idea to keep an eye on the noise figure at the front of the ADC, particularly for cases with
high-speed front ends. In addition, higher sample rates tend to aggravate other noise and distortion problems in the IC.
Backoff
Consider an 8-bit ADC used on the front end of a 64-quadrature amplitude modulation (QAM) receiver, oversampled by 1.5 times. This gives an SQNR over 50 dB. However, this references a full-scale sine wave. In a real application, there could be many uncertainties as to a receiver’s input level, easily varying the input to an ADC by 20 dB to 30 dB or more. If the
level to the ADC is allowed to vary this much, that level drop comes right out of the available SQNR. This is because the quantization noise power doesn’t change. In that sense, a good analogy to analog would be the noise figure (NF) of an amplifier on the front end. NF represents a fixed amount of additive white Gaussian noise (AWGN) that an amplifier will add at a given temperature. In the previous case, a 50-dB SQNR conversion becomes a 30-dB SQNR or less conversion. SNRs of this magnitude for a
higher order modulation such as 64-QAM enter the realm of not being able to ignore its effects. In other words, they contribute to link budget degradation. This may be palatable, but, in general, points to why automatic gain control (AGC) is commonplace to ensure that a steady level of backoff below full scale is delivered to the ADC. It is also worthwhile to leave a little headroom for interference and transient effects.
Numerical encoding
While it may sound odd at first, there are, in fact,
several useful ways to represent the number that is quantized at the output of an ADC or at a DAC input. Consider the basic binary code. The LSB here represents 2
0
, the next, 2
1
, etc. This is called natural binary. Unfortunately, for
N
bits, it can only represent integer numbers between 0 and
2
N-1
. Since the conversion process has a fixed full-scale input or output, it is more convenient to use that as a reference point. Such a scheme is called
fractional binary, and is achieved by simply dividing the natural binary number by
2N
. Now, the MSB has weight one-half, the next one-quarter, etc. The code represents every number from zero to
(1-2
-N
)
of full scale.
This describes how the quantized value corresponds to an analog value. Once we look past the actual conversion in or out, there are several other codes that turn out to be useful entirely within the digital domain. The reasons they become popular are because
they often provide straightforward interfaces to external circuits, and because complex mathematical calculations are often suited to forms that are more efficient. As such, some converters provide multiple possible digital input or output formats, allowing the designer to avoid the need to translate between formats. Some formats are more difficult to directly encode, and a translation, if necessary, may be easier. Here are some of the schemes:
•
Binary Coded Decimal (BCD).
BCD represents a
decimal (regular old base-10) digit by the 4-bit binary code that would correspond to it. Useful for display drivers that write and read decimal displays — that’s pretty much it nowadays. It used to be more popular, but now there are considerably fewer binary-challenged people than before. There is also a fractional BCD.
•
Sign-Magnitude.
We have conveniently ignored, up until now, the fact that waveform polarity can be positive or negative, and sometimes we don’t want to have to
bias it for the sake of a unipolar conversion. Working with dual polarity numbers is a natural operation with most signals of interest. This approach simply uses 1 bit to represent the sign (1 = negative) and the rest for magnitude. Easy, but not very computationally elegant.
•
One’s Complement.
A negative number is found simply by complementing all of the bits in the positive version. Again, not elegant. Note that both this and sign-magnitude have two versions of zero.
•
Two’s Complement.
The negative version of a number is the two’s complement of the positive. This is found by logically inverting the binary digits, and adding one LSB. Odd as this format sounds, it makes both addition and subtraction easy, although multiplication is still annoying. A very similar code, called offset binary, is the same, but with the MSB inverted (an easy option to provide).
Tune in next time
The second part of this perusal of these unique devices will delve into a few
more complex topics, and focus on some of the ideas and practical applications that drive their consideration. Examples include IF sampling and dithering. In addition, a summary of some of the more obscure specifications will be undertaken, which should help explain why only three or four different ADC or DAC data sheets can fit on a CD-ROM. O.K., maybe this is an exaggeration. But not many ICs warrant enough material to write complete books. Complex though it may be, a successfully implemented analog to
digital conversion process is the gate-opener to an indescribable (by one column) amount of sophisticated processing algorithms in communications.
Robert Howald is a staff engineer in the transmission network systems group at General Instrument in Hatboro, PA. He has a BSEE and an MSEE from Villanova University, and received his PhD from Drexel University. He can be reached at rhowald@gi.com.
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