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Mixing it up with OC-192 CMOS Transceivers
By Michael Green, Andrew A. Shapiro, Armond Hairapetian
Using new transceiver architecures, optical systems designers can accomplish new levels of integration, employ new packaging technologies, and improve jitter performance in 10-Gbps optical systems.
To meet the nearly insatiable demand for increased bandwidth to support global networks and the escalating migration toward e-commerce, fiber-optic networks are being deployed at an incredible rate. Fiber capacity started out in the network backbone for long-haul transport, and it will continue to dominate in that segment as it increases in capacity by progressing to higher frequency transmission standards. We're now seeing SONET transmission rates of OC-192, or nearly 10 Gbps, deployed in the backbone. Not long ago, this speed was a specialty, but it's expected to quickly become ubiquitous in the backbone and to begin moving out to the edge, and eventually to access networks.
With this proliferation of high-frequency fiber-optic data transmission, the cost and power of each critical component becomes a concern. Networking equipment designers strive to increase capacity while maintaining the same cost and form factor. In communications today, the competitive solution comes down to cost per bit, cost per bit-mile or per bit-kilometer, or other variants in the form of cost per packet, or cost per frame.
Another important trend in today's networks is the need for greater port density. As port densities go up in conventional technologies, the power required also goes up. Physical size limitations become a constraint and make it physically impossible to build a high port density device such as a cross-connect, without simultaneously increasing the level of integration and lowering power.
Transceiver concerns
One of the essential components of a high bandwidth optical communication network is the transceiver, required at every stage along the network - at every port in a router or switch and in optical transmission modules. Therefore, selecting the right transceiver is an integral part of the overall design process.
Traditionally, designers have employed GaAs, BiCMOS, or silicon germanium (SiGe) transceivers in optical communication designs. However, a new breed of CMOS transceivers is also entering the market, bringing new performance levels to OC-192 design. The challenge for designers now is choosing the right transceiver solution for their particular fiber-optic design.
The process matters
Conventional solutions for high-speed networks operating at 10 Gbps have been implemented using specialty processes such as GaAs, bipolar silicon, and SiGe technologies. These process technologies are expensive and require special fabs or equipment. Turning to CMOS, however, was not an option because it was long accepted that CMOS would not support high-frequency design.
With continued advances in smaller process geometries, CMOS is worth another look. Its maximum frequency increases and its power consumption decreases with each successively smaller line-width. By combining the increased cut-off frequency of CMOS at finer line-widths with advanced design techniques, it is now possible to implement 10-Gbps transceivers in a standard CMOS process and to produce these devices in volume.
As today's fiber-optic system designers well know, process technology can have a huge impact on the performance of a transceiver, especially as the industry moves to higher-speed operation. Let's look at the pros and cons of each of the process technologies.
After silicon, GaAs is the next most mature semiconductor device technology. GaAs transistors exhibit distinct advantages with respect to speed over silicon transistors. The peak electron velocity of GaAs is several times greater than that in silicon and is reached at a much lower value of electric field. GaAs transistors can operate at clock rates up to 30 GHz. GaAs has its drawbacks, however. Because GaAs wafers must be extremely thin to accommodate the material's low thermal conductivity, they can be extremely fragile, which can lead to lead high yield losses.
The wafers also are expensive to make, because the crystals must be grown in a toxic arsenic overpressure environment that is difficult to control. As a further drawback, GaAs does not support a high level of integration. As a result, it is typically used in military and high-frequency applications, as well as in power amplifiers and other analog devices, which feature a relatively small number of gates. The process is chosen when CMOS or other processes are not feasible.
BiCMOS also has been used successfully in selected high-speed communication devices, including transceivers. It is a fast, high-current process, but it has high power consumption levels. Although the process technology is similar to CMOS, BiCMOS is not a good technology for integrating high gate-count digital circuitry. As a result, high-speed analog circuitry has often been produced in bipolar silicon, while associated digital circuitry must be partitioned in separate CMOS ICs.
Furthermore, scaling conventional ion-implanted base transistors used in bipolar technology is becoming increasingly difficult, and they are generally used at speeds of 2.5 Gbps or below.
The SiGE approach
The third process technology considered for high-speed optical architectures is SiGe. SiGe is a high-performance technology that provides extremely high electron mobility in the 100,000-cm2/Vs range, which enables high-speed devices with performance nearly comparable to GaAs devices. It also supports higher levels of integration than either the BiCMOS or GaAs process technologies. SiGe can also be produced on standard CMOS processing lines, using a special process generally licensed from IBM.
On the down side, SiGe wafers are produced using extreme doping with germanium that requires stringent process control requirements and leads to a high defect density rate. Although SiGe is expensive and the process is difficult to control, several commercial suppliers are using it to successfully produce high-speed communication ICs.
An unconventional move
GaAs, SiGe, and BiCMOS processes have all been used to develop high-speed transceivers to date (despite their limitations and expense) because conventional wisdom said the mobility limitations of CMOS would not support high-speed devices above 5 GHz. This was true with larger process geometries, but is no longer the case.
The unity gain frequency (ft), or cut-off frequency, is the maximum frequency at which a transistor exhibits any amplification. Although the relationship between a transistor's ft and a circuit's maximum operating frequency strongly depends on a number of factors, characterization of the transistor ft is a convenient way to compare different technologies.
(1) 
Equation 1 is used to calculate ft: where m = mobility (approximately equal to 1450 cm2/Vs for an n-Channel MOSFET), L = geometry, and VDSAT = overvoltage applied to the device (roughly proportional to the supply voltage).
It is clear from the Equation 1 that scaling down CMOS technology allows significant increases in circuit speed. A typical scaling from one technology to the next decreases the minimum transistor length L by approximately the square root of 2, nearly doubling the maximum frequency at which the circuit can operate. A typical ft for 0.25-mm technology is 40 GHz; for 0.18-mm technology this value is 80 GHz. We would expect that the ft for 0.13-mm would nearly double once again.
As a result of progression to finer process geometries, CMOS is now a viable process for higher frequency devices. The ability to use CMOS vastly increases available production capacity, increases the level of integration possible, and reduces cost.
The CMOS process is preferable for numerous other reasons. It is mechanically strong; it is a good thermal conductor; it can be easily grown into large-diameter, ultra-pure, defect-free crystals; it forms stable insulating oxides and is nontoxic; and it is easily fabricated into millions of circuits per chip and hundreds or thousands of chips per wafer with high yields.
Given these advantages, it's no surprise that several transceiver manufacturers are moving away from the traditional SiGe, GaAs, and BiCMOS approaches, and launching CMOS transceiver ICs for high-speed fiber-optic designs. In fact, CMOS devices are already available for OC-48 and OC-192 applications.
Developing an OC-192 CMOS transceiver is not an easy task. At these data rates (10 Gbps), the difficulty of the design process increases significantly compared to OC-48 (with data rates of 2.5 Gbps). Two major challenges of OC-192 CMOS transceivers are control of the jitter parameters and packaging.
SONET jitter specifications are quite stringent. This ensures that the signals carried via fiber-optic lines over long distances are just as readable at the destination as they are at the origin. It also ensures interoperability among equipment from various vendors.
Taking care of jitter
The Bellcore jitter requirements center around the amplitude, rise and fall time, jitter, and bit timing of the clock and data signals on the line interfaces. Timing jitter is the short-term variation of a digital signal's significant instant from the signal's ideal positions in time.
SONET has three jitter specifications: jitter generation, jitter transfer, and jitter tolerance. To be considered Bellcore compliant, any piece of SONET equipment must meet all three specifications. The specifications are for system-level equipment, not for components or individual circuits.
Jitter generation is the amount of jitter that a serial interface can add to a data stream, assuming a stable reference clock. The SONET specifications limit this to a 0.1-unit interval of peak-to-peak timing jitter at the output of the terminal receiver. At OC-192, with its 100-picoseconds (ps) cycle time, the overall system must generate less than 10 ps of jitter - obviously, timing in the transceivers must be extremely accurate.
Jitter tolerance is the maximum amplitude of sinusoidal jitter at a given jitter frequency. This measurement identifies how much jitter a serial receiver can accept and still recover data within the bit-error ratio (BER) limits of the link. To accommodate the jitter that accumulates on a signal as it propagates from a serial source receiver, the receive jitter tolerance must be significantly greater than the combined jitter generation of the source and the media. For a jitter-tolerance specification, the more jitter tolerance a link can withstand while still recovering an accurate data stream, the better the receiver.
And finally, jitter transfer is the specification that describes how the spectral characteristics of jitter are modified as a signal passes through the equipment. This specification is important in long (usually 50 km or more) fiber-optic lines that require repeaters to maintain signal strength. The data coming in will always have jitter. If a single repeater amplified this jitter at a certain frequency by a factor a>1 (that is, the jitter transfer function exhibits peaking at this frequency), then n repeaters will amplify this jitter by an when the signal reaches its destination. For this reason SONET specifies jitter peaking of no more than 0.1 dB.
At the transceiver level, today's system designers should be concerned with choosing CMOS transceivers that minimize jitter generation and jitter transfer, while maximizing jitter tolerance.
Jitter causes
There are three primary causes of jitter in a fiber-optic communication system: noise, randomness of the data, and fluctuations in the signal that cause pattern-dependent jitter.
Let's start with noise. Any component, such as a CMOS transceiver, that dissipates power generates noise. Because of the high operating frequency, random noise coupling with the substrate generates additional random noise into the system with very low amplitude. Good design techniques combined with noise filter circuitry, isolation of the power supply, and the ability to test for noise immunity are the best avenues to minimize this source of jitter.
Clock and data coupling is also a major cause of jitter in a fiber-optic transceiver design. The fast serial data signal present at a receiver input and a transmitter output contains a large number of frequency components due to its random nature. A number of these signal components can couple back through the circuit board and chip substrate and, as a result, modulate the oscillator in the phase-locked loop (PLL), thereby adding random jitter to the timing circuitry. In a transmitter, this directly translates to additional jitter on the output serial data. This jitter can be addressed by minimizing coupling from the data signal to the voltage-controlled oscillator (VCO).
Pattern-dependent jitter
Another key concern for designers employing fiber-optic transceivers is pattern-dependent jitter. This is one of the main sources of errors in a digital transmission system, caused by distortion of the received signal. Pattern-dependent jitter becomes increasingly important at higher frequencies, as the cycle time becomes shorter. Distortion is manifested in the temporal spreading and consequent overlap of individual pulses to the degree that the receiver cannot reliably distinguish between changes of state.
There are two primary causes of pattern-dependent jitter. The first occurs when the rise and fall time of the CMOS transceiver's output data signal aren't quite fast enough to allow an isolated, single-bit pulse to reach its full amplitude. As a result, the single-bit pulse width will be significantly shorter than a full period (100 ps for OC-192 systems). Figure 1 shows a good eye diagram, and Figure 2 shows how this type of pattern-dependent jitter affects the eye diagram by causing a double edge.
A second source of pattern-dependent jitter occurs in systems that take output directly from the last multiplexer stage. In these designs, slight variations in the clock signal can create headaches. Ideally, a clock signal should be perfectly symmetrical, but in reality that's not always the case. Imperfections give rise to jitter.
From one rising edge to the next rising edge the timing will be accurate at 200 ps for the OC-192 half-rate clock, but the rising to falling time may not exactly equal the falling to rising time. Deviation in the 5-GHz clock, creating a duty cycle that is not exactly 50 percent, will result in a waveform with a short/long/short/long pattern in the data output signal (see Figure 3). If this variation were just 10 ps, creating a 90-/110-/90-/110-ps pattern, 10 ps of jitter would be generated, leaving no margin in the jitter generation spec for other system components. An additional retiming stage, although more challenging, can improve the jitter characteristics.
With a thorough understanding of these fundamental causes of jitter, it is possible to design CMOS transceivers that contribute as little jitter as possible to system-level performance. This is an important characteristic for selecting a CMOS or other OC-192 transceiver.
Packaging it together
In the traditional commercial semiconductor market of a few years ago, electronics packaging was seen largely as a resistance drop from the sophisticated silicon IC to the circuit board. More recently, as CMOS semiconductor speeds approached and passed the 1-GHz regime, the inductance and capacitance of the package started to become a part of post-IC design consideration. At high frequencies, a large portion of the electromagnetic (EM) wave travels on the surface or outside of the conductor lines. With the OC-192 SONET specifications becoming a reality at about 10 GHz and the next generation at about 40 GHz, the entire package design strategy must change if designs are to be successful.
Traditionally, designers have employed OC-192 transceivers housed in ceramic packages in their fiber-optic architectures. But, as performance levels started to increase, the demand for new chip-scale package approaches arose.
As designers begin to look at CMOS transceiver solutions, they now have a new set of chip-scale packaging options. One package that is gaining popularity in fiber-optic transceivers is the flip-chip package.
Under the flip-chip approach, the semiconductor die has small bumps, usually of gold or solder, plated on the upper surface (requiring some change in metallurgy). The die is then inverted (flipped) and soldered to the package. Figure 4 shows a typical flip-chip arrangement.
Flip-chip advantages
Flip-chip packaging has five distinct advantages. The first benefit is that the electrical parasitics associated with wirebonds diminish almost completely, reducing inductance and resistance with a slight addition to capacitance. Additionally, for high-speed signals, the pad may be placed near the gate and the signal may be dropped directly from the gate pad to the substrate through to the printed circuit, with essentially zero trace length.
The second benefit is thermal dissipation. Thermal dissipation can be improved because heat may now be more easily removed from both sides of the die. The bumps on the die provide a much better heat path than wirebonds or molding compound. A heat sink can be attached directly to the back of the chip, giving a second much better thermal path.
The third benefit is cost. Flip-chip packaging is inherently more cost effective from a processing point of view.
Reliability is the fourth advantage with flip-chip packaging. The solder interconnect is larger and more robust than a 1- or 0.7-mm wire. It should be inherently less susceptible to chemical attack and to mechanical stress.
The final advantage is size. As designers pack more and more ports into their system architectures, size becomes an increasing concern during the design process. Flip-chip packages allow designers to reduce overall die and package size and, in turn, reduce the overall size within a system design.
A look ahead
In traditional optical module design, the module includes an optical/electrical interface, with the transponder, clock, and demultiplexer functions on the input side, and laser driver, clock multiplication unit (CMU), and multiplexer on the output side (see Figure 5). At OC-192 speeds, heat dissipation, noise, and jitter tolerance become significant challenges with this traditional approach, though it is still a viable alternative.
The higher levels of integration possible with CMOS can decrease power dissipation by combining functions and reducing the number of chips. An integrated chipset, which houses transceiver, clock data recovery (CDR), and CMU functions can reduce power dissipation and associated heat problems, which in turn enables a higher performance class of communication system with improved performance metrics. All this without increasing power requirements or physical size.
Additionally, increasing integration could significantly reduce design complexity and power consumption for these optical modules. One step that is gaining ground is developing a transceiver with integrated CDR and CMU functions on chip. The next logical step beyond that would be to also include the system-level functions, such as framer functions, on the transceiver.
Increasing integration levels could eliminate additional components currently outside the optical module. This is one of the most promising avenues for future improvements in transceiver design to continue to reduce the cost per bit and increase overall system capacity without increasing physical system size.
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