Feature

Bluetooth has been one of the most talked about technologies in the communication market. With its promise to connect mobile devices around the world, this emerging short-range technology has landed the support of players of all sizes in the communication, consumer electronics, and computer communities.

However, despite all the hype, Bluetooth is not an easy technology to design. In fact, it is arguably the most challenging application, in terms of cost, to emerge for RF technologists.

Commercial RF applications introduced in the 1990s (such as cellular, cordless, and Global Positioning System [GPS] systems) brought with them a major shift in terms of application technology. The high-performance, "no cost spared" radio for the military market of the 1980s was based on high-performance discrete designs, controlled-impedance-line packages, GaAs semiconductors, and gold-plated alumina hybrids. These techniques ultimately had to be abandoned for silicon bipolar CMOS (BiCMOS), plastic packages, and FR4 printed-circuit boards (PCBs) in order to meet the type of cost profile associated with the cellular marketplace.

The new century offers a large opportunity for RF technologists -- the combination of the Internet with mobility or, in engineering speak, wireless data. Bluetooth is at the heart of this new opportunity and with marketing projections of 700 million units in 2005, most major semiconductor players are showing an interest.

The big Bluetooth challenge is the projected radio cost curve that is going to accompany the market growth (see Figure 1). By 2005, the average standard price of a Bluetooth radio is projected to be at $3. This will be for a component operating at 2.4 GHz (not an insignificant specification) and containing an agile frequency synthesizer. This cost figure means that, like the GaAs-plus-alumina hybrid before it, the present silicon BiCMOS RF technology platform has to be ditched for a more cost-competitive alternative.

The best semiconductor option for achieving the cost demands of a Bluetooth radio is CMOS, which has benefited from cost reductions driven by digital requirements such as higher integration density and larger wafers.

Choosing a process

Choosing a process technology is a challenging task for chip designers. Chip designers must sort through hundreds of process technologies to determine the proper solution for their Bluetooth designs.

The choice of a process, however, does not only impact the chip designer. This decision also has an impact on the system designer. Different processes deliver different performance levels, different trade-offs, and different price points. All of these play a huge role in the development of Bluetooth-enabled systems. Therefore, it is crucial that today's system designers evaluate process technology when selecting a chip for their Bluetooth system.

As with general RF chip design, there is a flurry of processes to filter through when evaluating Bluetooth solutions. For example, a variety of chip designers are employing BiCMOS to develop RF chips for Bluetooth applications. But, as stated above, the traditional RF processes may not be the best for meeting the price points demanded by the Bluetooth design community. Therefore, some IC design houses have started exploring standard and exotic CMOS processes for Bluetooth applications.

Of course, there are a variety of CMOS solutions. Despite this, three processes have emerged as clear leaders in the CMOS arena. These include bulk CMOS, RF-added CMOS, and silicon-on-insulator (SOI).

Table 1 contains a simple comparison of the three main CMOS processes. Bulk represents a digital CMOS process, nonepitaxial without any extra "RF friendly" enhancements. CMOS (RF added) covers an option that is now being presented more frequently by technology vendors. The final process, SOI, is the most exotic of the three processes, adding an insulator layer to the traditional CMOS approach to increase isolation in an RF design.

Comparing CMOS approaches

Since CMOS is quickly emerging as a viable solution for developing RF front ends, designers who are employing Bluetooth RFIC solutions need to quickly get a grip on differences between the different CMOS process options. To assist designers, a more detailed look at the SOI and bulk CMOS processes is in order, beginning with SOI.

During the past few years, SOI technology has been hyped as one of the next big processes in the RF design community. At the heart of the SOI process, which is supported by at least one Bluetooth RFIC developer, is a silicon dioxide (SiO2) insulating layer, which is added to a standard CMOS process.

The insulating layer provides many benefits to the Bluetooth system designer. By including the insulating layer, RFIC designers can develop chips that reduce drain capacitance and deliver lower threshold voltages. The insulating layer also removes the potential hazard of latch-up and reduces substrate noise coupling. In addition, the insulating layer provides higher isolation in the chip design, allowing manufacturers to embed more functionality on the same piece of silicon. To the Bluetooth system designer, this translates into higher integration, improved performance, and lower power consumption in an RF chip.

During the evaluation, an RF chip being developed using a 0.35-micron SOI process, on-wafer S-parameter measurements were taken on a 300-micron field-effect transistor (NFET) and coplanar mount at a bias point of 1.5V and 11.5mA. During the measurement, the NFET achieved a Gmax of 15.7 dB at 2.4 GHz. This is a very strong figure for producing low-noise amplifiers (LNAs), power amplifiers, and voltage-controlled oscillators (VCOs) employed in RF front-end designs (see Figure 2).

The SOI process, however, does have its share of problems. SOI FETs tend to feature lower output impedance than their bulk CMOS counterparts, which complicates RF and analog circuit design. This effect is related to the "kink" observed in the SOI device voltage-current (IV) characteristics, which is difficult to model accurately in electrical simulators used by the designer for chip design.

The most tangible drawback of SOI technology for Bluetooth radio implementation is cost. Based on a typical core radio area of 10 mm2, the cost of an RF chip developed using an SOI process can be up to twice as expensive than a chip developed using a bulk CMOS process.

Bulking up

After exploring the pluses and minuses of the SOI approach, let's examine the bulk CMOS approach. A nonepitaxial 0.25-micron bulk CMOS process has been extensively characterized on-wafer for developing RFICs that support Bluetooth applications. The Gmax extracted from the S-parameters of the RF devices manufactured on this process is contained in Figure 2 for the same bias condition as in the SOI case -- 1.5V and 11.5mA. Based on the numbers, the Gmax achieved using this process is 15.2 dB, which is 0.5 dB lower than the Gmax obtained by the SOI process.

But, even though the bulk CMOS process loses on the Gmax figure, it beats out the SOI process on output impedance. Specifically, the bulk CMOS process achieves a higher output impedance, curbing the kink and conductance problems encountered by chips developed using the SOI approach.

Passive performance

Evaluating S-parameters of active devices is a start for designers trying to get a grip on the process technology used to develop a Bluetooth RFIC. It is equally important for designers to evaluate the impact that the process technology has on the quality, tolerance, and repeatability of passive components.

There is no question that RF system designers are looking for any solution possible to reduce the number of passive components in their designs. By reducing the number of passives, designers can free up valuable PCB space, which can be employed to add new functionality or shrink the overall size of a system.

Planar spiral inductors are one of the main targets for integration. By integrating these inductors on-chip, designers can reduce bill of materials as well as deliver higher yield. On the performance side, on-chip spiral inductors exhibit much tighter tolerances (2%) compared to those of external wound components at RF frequencies (10%).

There are some other performance benefits to moving the spiral inductor on-chip. First, by housing the inductor on-chip, the need for an external inductor is removed, increasing the self-resonant frequencies and avoiding unwanted oscillation in the Bluetooth RF front end. Additionally, by integrating the inductor, chip designers can place multiple inductors in a symmetrical layout.

The effective boost in amplifier gain delivered by an on-chip inductor's quality factor (Q) is especially important for CMOS since it helps to compensate for the inherently low transconductance of FETs compared to bipolars at a given bias current.

Unfortunately, the available Qs demonstrated for bulk CMOS inductors have been poor, with typical values of 3 and 4. Work recently carried out in this area has concentrated on optimizing the spiral inductor design within the constraints established by the CMOS process. Some useful Q values are now being obtained on straight digital CMOS processes -- that is, nominal thickness, aluminum top-layer metal with a nonepitaxial substrate.

One measured example is shown in Figure 3 for a 2-nH inductor. The resultant Q of almost 7 at 2.5 GHz represents a usable value for wireless circuit applications. The dispersion in the resistance plot over frequency indicates that the Q is being degraded by series and shunt (or substrate) loss.

Varactors

There are a number of different varactor options provided by standard digital CMOS technology. Two of the most popular options are Ptap in N-well diodes and gate-plus-drain-source-connected FETs. One implementation option that is now popular because of its good RF performance is the accumulation mode NFET (N+ in N well). Figure 4 contains measured results for this device and the following points are worthy of note:

• Measurements taken at 2.4 GHz and with an RF input power of -15 dBm.

• Capacitance range of 2:1 for a voltage change of 1.5V. This range in turn leads to high voltage-controlled oscillator (VCO) gain figures at RF frequencies and the removal of the need for special VCO trimming techniques. VCO production trimming, typically via laser burn, is too expensive an option for Bluetooth radios. On-chip trim circuitry is another option but this entails extra current consumption.

• Accurate modeling of varactor operation is made through Tanh function.

• Minimal Q variation over operating range as a result of the series resistance decreasing as the capacitance increases with applied bias voltage. This is in contrast with junction-diode-based varactors that exhibit maximum capacitance variation as forward bias (and hence poor Q) is approached.

• Good minimum Q of 38 that means the resistance-capacitance (LC) tank circuit's performance will be limited by the on-chip spiral inductor.

LNA circuit example

One of the biggest hurdles for the CMOS process is the low-noise amplifier (LNA). Up to this point, designers have struggled with developing LNAs using a CMOS process that can handle 2.4-GHz operation.

But, things are starting to shape up. A two-stage LNA for unlicensed 900-MHz application has been designed in a pure digital CMOS, 0.25micron process without any of the technology RF options. The circuit was incorporated in the corner of a larger test chip that included other RF circuits plus active and passive devices for RF on-wafer probing.

Table 2 contains a summary of the device performance at 900 MHz while Figure 5 shows gain and noise-figure (NF) variation over frequency.

Here are some highlights from the 900-MHz LNA circuit:

• This is a two-stage design. The first stage features a cascade topology with resistive load and noise-match optimization via the common-source bond wire to ground. The second stage is a shunt series amplifier configuration that provides extra gain and a 50- ohms output impedance.

• An on-chip bias circuit provides constant transconductance bias with temperature (equivalent to bipolar PTAT circuit) to the RF stages. This includes a start-up circuit and noise filtering.

• Input and output matching is off-chip and uses standard 0603 lumped components. Both matches are for gain -- no special effort has yet been made to provide the LNA input with the optimum reflection coefficient for minimum NF.

• The circuit is packaged with FR4, chip-on-board technology.

• The input pad to the LNA has its own separate substrate shielding pad to ground. This is important for a bulk CMOS LNA since the equivalent substrate resistance of 300 ohms is directly in parallel with the circuit's input and will impact NF. The same point also holds for CMOS power amplifiers (PAs), where this parasitic shunt resistance will degrade efficiency if not removed.

Although the results quoted are for 900 MHz rather than 2.4 GHz, bear in mind that the NF requirement for a Bluetooth LNA is typically in the region of 6 rather than 3 dB.

The final stretch

Applications such as Bluetooth with very aggressive cost targets have caused RFIC designers to investigate pure digital CMOS processes for radio implementation. Initial results on device and RF block performance are encouraging. Deep submicron CMOS devices can provide impressive RF performance in terms of noise, linearity, and gain. The results for passive components show that careful design can lead to more than adequate Q. However, doubts about circuit-to-circuit isolation still exist, and the big challenge of complete Bluetooth radio and baseband integration on a single die has yet to be accomplished. More investigation is also required into the whole area of CMOS RF circuit yield and how this will impact the cost competitiveness of fully integrated radio and baseband chips.

Acknowledgements

The author wishes to acknowledge the following people: Brian Brunn at Rocket Chips, Inc. for design and measurement of inductors and varactors presented; Mark Norton for design of the LNA COB module and LNA measurements; Martin Naughton for design of the CMOS LNA circuit; Dan Breen for input to CMOS LNA circuit design; and Bob Tait for providing Bluetooth radio ASP projections.

About the Author

Michael McCullagh is the RF technical director of Parthus Technologies, Inc. He can be reached at michael.mccullagh@parthus.com.

Figure 1: Projected Bluetooth radio ASP to 2005.
Figure 2: The Gmax extracted from the device's S-parameter.
Figure 3: Q factor, series resistance, and rectance for a 2nH spiral inductor
Figure 4: Capacitance, Q factor, and series resistance change for accumulation mode NFET varactor.
Figure 5: Gain and noise figure performance for 0.25-UM CMOS LNA.

Table 1: Bluetooth RF CMOS Options
Table 2: Performance of a 0.25-um CMOS LNA

Return to the Table of Contents