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DSP Improves Power, Performance in Next-Gen Comm Designs
By Robert Keenan, Editor-In-Chief
New processor employs dual-MAC architecture to achieve up to 400-MMAC performance with as low as 80-mW power dissipation in 3G handset and VoIP designs
Digital signal processors (DSPs) still remain the heart and lifeblood of many modern communication systems. Therefore, as individual segments within the communication market evolve, there is a clear call for DSP technology to adapt and change as well. In particular, developers of third-generation (3G) wireless handsets and voice-over-IP (VoIP) solutions are searching for DSPs that deliver lower power consumption and significantly better performance. Answering these pleas, Texas Instruments has unveiled the TMS320C5510 (C5510) DSP.
Similar to previous TI DSPs, the C5510 (see Figure 1) is targeted at the communication market. In particular, this DSP, which is currently sampling at 320 MMACs, is designed to meet the requirements of emerging 2.5G and 3G handsets as well as VoIP infrastructure and terminal designs.
The C5510 is the first product to house the TMS320C55x (C55x) DSP core, which was launched in February 2000. By using this core, the new DSP offers a dual-multiply-accumulate (MAC) architecture that features a 32-bit programming bus, three 16-bit read buses, two 16-bit write buses, and six 24-bit address buses.
The two MAC units within the C5510 DSP are designed to operate in parallel. This allows the MAC units, each capable of 17 x 17-bit multiplication in a single cycle, to operate simultaneously. By working in parallel, the MAC units allow the C5510 to execute instructions faster and to quickly return to a standby mode or power-down state, thus improving performance and reducing overall chip power consumption.
Flexible instruction set
The C55x core also equips the C5510 DSP with a flexible instruction set that system designers can scale from 8- to 48-bit, depending on their needs. Therefore, designers can adjust the instruction set to execute code more efficiently within the DSP. For example, lighter tasks can be run in an 8-bit instruction while complex tasks can be performed in a 48-bit instruction. This gives the designer the flexibility to optimize the overall DSP performance, improve DSP efficiency, and reduce the overall power consumption of the processor.
The instruction set performs 32-bit program fetches from internal and external memory and queries instructions for the instruction buffer unit. The instruction buffer unit then decodes the instructions and directs tasks to the address unit and data unit resources. The DSP core also includes a predictive branching capability to avoid pipeline flushes on execution of conditional instructions.
Overall, by using the C55x core, the C5510 DSP can achieve a performance of up to 400 MMACs. At the same time, the new DSP can attain an overall power dissipation figure of 80mW at 320 MMACs. According to TI, this power dissipation figure is up to six times better than the previous C54x family of DSP products.
Memory capabilities
Similar to older TI DSP families, the C5510 delivers a good amount of on-chip memory support. In particular, the new processor offers up to 160 kwords of on-chip static RAM (SRAM). This SRAM block benefits designers of 3G and VoIP systems by minimizing the power-hungry off-chip accesses.
Although on-chip memory capabilities are ideal, some applications require additional memory. To accommodate these needs, the C5510 has an external memory interface (EMIF) that provides glueless access to asynchronous memories, such as EEPROM and SRAM. This same interface also links the DSP with high-speed, high-density memories such asynchronous dynamic RAM (DRAM) or synchronous-burst SRAM (SBSRAM).
To provide hot processor access to internal memory, the C5510 features an enhanced host-port interface (EHPI). The EHPI is a 16-bit parallel interface that can be configured in either multiplexed or nonmultiplexed mode.
The C5510 also sports three full-duplex, multichannel, buffered serial ports that connect the DSP to a variety of industry-standard serial devices. Additionally, these ports allow the DSP to achieve multichannel communication with up to 128 separately enabled channels.
Tool support
When dealing with any DSP, tools are king. Thatıs why it is critical for designers to evaluate the tool set a manufacturer is offering with its processor.
Similar to previous TI DSPs, the C5510 is equipped with a strong tool set. Specifically, the new DSP is supported by TIıs eXpressDSP real-time software tool set. This set includes the Code Composer Studio integrated development environment (IDE), the DSP/ BIOS tools, and the TMS320 algorithm standards. The eXpress tool set also includes debuggers developed by third-party manufacturers. One of these third-party manufacturers is TIıs Telogy subsidiary, which develops software specific to VoIP applications.
The compiler still stands out as the biggest headache for todayıs communication design engineers. Past compiler designs have been extremely inefficient, forcing designers to turn away from friendly C/C++ code development toward developing algorithms using traditional hardware description language (HDL) approaches.
During development of the C5510 DSP, TI spent a significant amount of time producing a compiler for its new DSP solutions. Specifically, TIıs compiler was developed in conjunction with the C55x core to optimize the performance of this compiler solution. By doing this, TI claims it has developed a compiler that develops efficient C code for the C5510. Using this compiler, TI says designers can develop code that is 30% smaller than C code developed for the TMS320C54x DSP products. Further details on compiler performance will be released later this year.
An application plug-in software tool is also available for designing data converters that work in conjunction with the C5510 DSP. This new tool, which plugs into Code Composer, cuts configuration time for TI data converters used along with the C5510.
Pricing
The C5510 will be delivered in a 15- x 15-mm microStar ball grid array (BGA) package in both 160-MHz and 200-MHz versions. Samples of the 160 MHz products are currently available. Production quantities of the 160-MHz version and samples of the 200-MHz version are slated for the fourth quarter of 2000. Pricing for the 200-MHz version is $40 per chip in 10,000-unit quantities. For more information on the product, contact Texas Instruments at Literature Response Center, P.O. Box 954, Santa Clara, CA 91380. Phone: 800.477.8924, ext. 4500.
URL: www.ti.com.
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