Feature Article

Power control in IS-95A

A mobile phone network consists of base stations and multiple mobiles. The base station transmits control messages and voice traffic to the mobiles on the 1.23-MHz bandwidth forward link. The mobiles send control messages and voice traffic to the base station on the separate 1.23-MHz reverse link. While, both the forward and reverse links require power control, the main need for power control arises in the reverse link.

The reverse link requires power control primarily to solve the ýnear-farý problem. All handsets transmit on the same frequency channel at the same time but with different codes. Therefore, one handsetýs signal may interfere with the others. A mobileýs received signal quality at the base station is inversely proportional to the power of the interference from other mobiles.

The near-far problem arises when two mobiles transmit at the same power but at different distances from the base station. Due to different propagation losses, the transmissions can arrive with very different received powers. The mobile near the base station, which has a high received signal power, greatly interferes with the distant mobile, which may not be detected.

Power control on the reverse link also deals with the rapidly changing attenuation characteristics of multipath fading channels common in urban environments. In these environments, the received power of a typical wireless channel varies dramatically with time for specific velocity and multipath characteristics.

To solve problems encountered in urban environments, the power control algorithm ensures that the received power levels of all handsets are the same at the base station. The algorithm does this by controlling the mobileýs transmit power. Handsets are commanded to transmit at a higher power level when their received power is low, such as when they are far from the base station. Additionally, handsets are commanded to transmit at a lower power level when their received power is high, such as when they are near the base station.

To control power in this manner, the algorithm continuously monitors the received power of each mobile and continuously adjusts its transmit power to achieve predefined performance levels, such as frame error rate (FER).

Traditional design process

The traditional design process for many new products, such as cellular equipment, often starts with the creation of a high-level diagram or schematic for the whole system. Then, engineers must partition the problem into components, such as programmable digital signal processors (DSPs), digital ASICs, analog/mixed-signal ASICs, and RF components. Specifications for each component and the interfaces between them are usually documented on paper. Teams of hardware and software engineers work separately on individual components using low-level structural and circuit-level tools such as assembly code, hardware description language (HDL) products, and PSpice tools.

Low-level tools such as PSpice products are slow in terms of development and simulation, and as a result, engineers only perform limited testing of the components before implementing prototypes. Problems can arise due to ambiguous and miscommunicated specifications. Also, since low-level and circuit-level tools cannot be integrated easily, the subcomponents are not simulated together, leaving the system as a whole untested. In particular, unforeseen interactions can occur among the analog, digital, or control logic components, and can prevent the whole system from meeting its specifications.

With graphical block-diagram and state-machine system-level design tools, an engineer can quickly specify a top-level architecture for the whole system that matches the conceptual de-sign. Built-in blocks for common signal processing and communication operations allow designers to build a high-level design quickly. Designers can split the design into components to be worked on by each team member.

Using the system-level design approach, all team members can use the same tools, creating a system-level design of individual analog, digital, or control logic components. With system-level design, designers can perform global optimizations by trying many different solutions. Block diagrams let designers accurately model the concurrency of the multiple components and the complex timing relationships present in any real system.

Once the components have been designed and tested individually, engineers can integrate them together and test the whole system to create a validated design. Only then do team members perform low-level structural design using assembly code, HDL, and PSpice. The system-level design can be used as a high-level executable specification, which can be compared against the low-level structural design. In this way, the risk of errors is substantially reduced, resulting in fewer failed designs and shorter product cycles.

A real-life example

To better illustrate the advantages of the system-level design approach, consider the development of power control algorithms for IS-95A systems. For example, letýs use graphical block diagram and state diagram system-level tools to design and simulate the power control algorithms of IS-95A.

Before designing and simulating the algorithm, itýs important to understand how the handset and base station communicate in a wireless network. This understanding can be found in the channel structure described in the IS-95A CDMA specification.

The forward link, transmitted from the base station to the mobile, occupies a 1.23-MHz bandwidth and consists of a number of logical channels separated by unique orthogonal Walsh codes (see Figure 1a). The base station uses the sync and paging channels to transmit control messages to the mobiles and uses the forward traffic channels to carry the voice conversation to each mobile.

The reverse link occupies a different 1.23-MHz bandwidth and consists of a number of logical channels separated by unique pseudo-random noise (PN) codes (see Figure 1b). The mobiles use the access channels to transmit control messages to the base station and use the reverse traffic channels to carry the voice conversation back to the base station.

Reverse link power control

Reverse link power control manages the transmit power on a mobileýs access channel and reverse traffic channel. The reverse link does not use orthogonal Walsh codes to separate the mobilesý signals. Instead, it separates signals from different mobiles purely by their PN or long code, a distinct, 41-bit code that is used to scramble data before transmission. Co-channel interference is therefore a bigger problem than on the forward link, which uses orthogonal Walsh codes. A more complex power control strategy is required, including both open- and closed-loop control.

Open-loop power control

In open-loop power control, the mo-bileýs transmit power is determined by measuring the received signal strength of the base station and estimating the forward link path loss. Assuming a similar path loss for the reverse link, the mobile uses this information to determine its transmitter power.

The first time a handset transmits, it will do so on its access channel as a reply to a message on the paging channel, or to place an outgoing call. Due to the near-far problem and the risk of interfering with other mobiles in the cell, the handset initially transmits at a low power. It then makes successive attempts (or probes) to be heard, gradually increasing its power each time until the base station detects the message and acknowledges it.

The handsetýs initial mean output power is a function of the base stationýs received power plus system parameters in the initial access parameters message sent on the paging channel. These parameters include nominal power (Nom_Pwr), initial power (Init_Pwr), step increase in power between access probes (Pwr_ Step), and the number of access probes allowed in a sequence (Num_ Step). The formula is given by Table 1.

When designers start to create a complex system in this manner, system-level design tools allow them to begin at a high level and progressively add detail and fidelity to the design. For example, engineers can start designing a link-layer protocol without the physical layer in place, then add that layer after testing their protocol. As another example, engineers can design the channel coding operations with a simple additive white Gaussian noise (AWGN) channel and then add a realistic fading channel later. Engineers can also design these components in parallel. In our example, we will start with the control logic for the power control algorithm without the channel.

Figure 2 illustrates a state machine describing the control logic that would typically be coded in software on a microcontroller. Graphical state machine design tools, like the ones depicted in Figure 2, allow the description of system states, substates, and events that cause the transitions between them. This can greatly clarify the description of complex algorithms.

Comparing system states

Animated simulations also allow designers to visually compare system states with system signals. Figure 2 highlights one system state, which contains two substates. Arrows are used to describe transitions between states and the labels on the arrows show the event that causes the transition. Data processing can be included in the body of the state or after the transition label. In Figure 2, when the mobile first enters the access_probe substate of the system_access state, it:

• Sets the transmit power using the formula
• Enables the transmitter
• Starts a timer
• Waits in the Access_Probe substate.

If the mobileýs power level is sufficient for reception at the base station, the base station transmits an acknowledgement on the paging channel. This message on the paging channel, labeled as the event BS_ Response, triggers the system to leave the system_access superstate, disable the transmission on the access channel, and move to the reverse traffic channel control state below.

If a reply is not received, the Time_Out event generated by the timer causes the system to leave the Access_Probe substate, increase the Sum_Access_Probe_Correction variable by Pwr_Step, and increase its Num_Access_Probes counter by one. The system then re-enters the Access_ Probe state, where the new value of the Sum_Access_Probe_ Correction variable is used to modify the transmit power. It repeats this operation until the base station replies or the maximum allowed number of access probes Num_Step is exceeded.

In Figure 2, we see that when the Num_Step threshold is reached (Num_Access_Probes>=Num_Step), the system enters the wait state. Here, the access transmission is disabled, the probe power correction and probe count variables are reset, and the mobile starts its timer to wait for a random period given by another system parameter.

Once the mobile begins to transmit on the reverse traffic channel and receive on the forward traffic channel, a fast, closed-loop power control algorithm is employed. Here, the base station measures the handsetýs received signal power and commands it to increase or decrease its transmit power so that the reverse traffic channel meets a specified FER. Example minimum quality levels are a 1% to 2% FER and a maximum of three to four consecutive frame errors.

Closed-loop power control

Closed-loop control involves both the forward and reverse traffic channels, so successful optimization of the algorithm requires the simultaneous simulation of both these physical layer channels. To add the physical layer to a design, an engineer can use libraries of pre-built blocks for DSP and communication operations provided with block-diagram system-level tools.

The reverse traffic channel, shown in Figure 3, is built from blocks that perform cyclic redundancy check (CRC) generation, convolutional encoding, symbol repetition and interleaving, spreading, modulation, and filtering. Blocks can be colored to highlight the different sample rates in the system.

Blocks colored blue, like the interleaver and convolutional encoder, execute at the 50-Hz frame rate. Blocks colored red execute at the higher 19.6-kHz symbol rate, and blocks colored yellow execute at more than one sample rate. Many different sample rates can be visualized this way. The values next to the block ports denote the signal width. Here we can see that the frame size is 576 symbols.

Closed-loop power control can be further subdivided into inner and outer loops. In the outer loop, the base station starts with a target FER and a target bit energy-to-noise spectral density ratio (Eb/N0) required to achieve the target FER. The base station then continually measures the FER and adjusts the threshold Eb/N0 accordingly.

Base station algorithm

Both the forward and reverse traffic channels are subdivided into 20-ms frames. Each frame is further subdivided into 16 power control groups (PCGs) lasting 1.25 ms. In the inner loop, the base station measures the received Eb/N0 of each mobile for every PCG and compares it to the target threshold calculated by the outer loop. If the Eb/N0 is less than the target, the base station commands the mobile to increase its transmit power. If the received power is higher than the target, the base station commands the mobile to decrease its power.

The base station communicates these commands to the mobile via the power control subchannel of the forward traffic channel, as shown in Figure 1. This subchannel transmits by inserting power control bits into the traffic channel at the PCG rate using a technique called ýsymbol puncturing.ý The bits are inserted after the long code scrambling, just before Walsh code spreading. There are 24 symbols in one PCG in the forward traffic channel and therefore 24 possible locations for the power bit. The location changes with every PCG and is specified by the last 4 bits of the long PN code in the previous frame.

The handset extracts the power control bits using the same long PN code bits. If a 1 bit is received, the mobile reduces its transmit power by 1 dB. If a 0 bit is received, the mobile increases its transmit power by 1 dB. Now the mobiles uses the formula in Table 2. to calculate its transmit power.

Figure 4 shows the mobileýs control logic, which adjusts its transmitted power as a function of the power bit. On entering the traffic channel control state from the System_Access state, the traffic channel is enabled. In the conversation substate, the transmit power is set using the previously mentioned formula. On every PCG clock event, the system exits the substate and looks at the value of the power bit stored in Power_Bit.

If the value equals 0, the Sum_Power_ Bit_ Correction variable is incremented by 1 dB. If the value equals 1, the Sum_ Power_ Bit_ Correction variable is decremented by 1 dB. The system then returns to the conversation substate, where the new value of the Sum_Power_ Bit_ Correction variable is used.

System simulations

With the control logic, reverse traffic channel, and forward traffic channel in place, a designer can run simulations to test the algorithm. Here, the designer will add a channel with three Raleigh fading multipaths at a Doppler frequency of 40 Hz plus AWGN at -84 dBm.

In Figure 5, the top axis of the oscilloscope shows the mobileýs transmit power in yellow, the mobileýs receive Eb/N0 in purple, and the Eb/N0 threshold in light blue. The lower axis shows a frame rate clock in yellow where each edge marks the start of a frame, the value of the power bit sent on the power control subchannel in purple, and the PCG rate clock in light blue.

Due to fading, the received Eb/N0 varies. Whenever Eb/N0 is greater than the threshold, the base station sets the power control bit to 1 and the mobile correspondingly decreases its transmit power. Whenever Eb/N0 is less than the threshold, the base station sets the power control bit to 0 and the mobile correspondingly increases its transmit power. These power adjustments ensure that the mobile maintains an acceptable FER while minimizing its transmission power.