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Ensuring Loop Stability in VCO Tuning
By Brendan Daly
Several techniques are available to counteract the inherent tuning instabilities of VCO-controlled communication products.
Wideband voltage-controlled oscillators (VCOs) feature inherent nonlinear tuning sensitivity (KV). This presents a stability issue for any system where it is necessary to employ a wideband VCO for frequency coverage, such as in cable TV systems. A versatile, programmable charge pump is an approach to compensate for the nonlinearity of a wideband VCO.
Each element of phase-locked loop (PLL) systems has an overall effect on stability in VCO implementations. In theory, a programmable charge pump can be used to ensure loop stability when factors such as VCO KV are nonlinear. Other critical factors in PLL design include lock time, phase noise, and reference spurs. All of these can be degraded by variations in loop stability.
The closed-loop bandwidth (CLBW) is defined as the 3-dB cutoff frequency of the response, so it is directly proportional to the closed-loop gain (CLG). A good question to ask at this point is what exactly is so unappealing about variations in open- and closed-loop bandwidth that a wideband VCO contributes in the loop. For one thing, CLBW has a direct relationship to loop settling time. As a rule of thumb, if the CLBW doubles, the loop settling time is halved. Many system designers cannot afford the luxury of the wide settling time variation that can result from the nonlinear VCO KV.
Noise is another factor that is affected by CLBW. Radio designers have integrated phase-noise specifications that must be met in their applications. Variations in CLBW mean that the loop filter will begin to attenuate noise at different offset frequencies, which directly leads to differing values of integrated phase noise. Attenuation of reference spurious signals will also be affected by variations in CLBW. It is intuitive that the wider the loop bandwidth becomes, the less attenuation will be present at the reference spur.
Unfortunately, there is a very real possibility that the loop will become unstable, rendering the entire PLL useless for its intended application. The example application does not become unstable, but it will be shown how close it actually comes to becoming an unstable system. Instability is defined as having an open-loop phase of 180 degrees at the open-loop unity gain frequency.
PLL theory
Without getting too deep into theoretical realms, a PLL is a closed-loop negative-feedback system. From a theoretical point of view, it is necessary to look at the PLL basic components and how they are related. These basic blocks from which the transfer function will be derived are the phase-error detector, the loop filter, the VCO, and the feedback factor N. Figure 1 is a block diagram of a PLL system and shows the following elements:
The phase-error detector, KD, generates an analog voltage or current that is proportional to the phase error between its inputs. Its units are volts/radian.
The loop filter, Z(s), is designed with specifications such as bandwidth, phase margin, settling time, and loop order in mind.
The VCO, KV/s, outputs a frequency that depends on the magnitude of the control voltage applied at its input. Since it acts like an integrator, its units are radian/volts*sec.
The one block that has not been mentioned yet is the 1/N block, which is the N divider value in the synthesizer.
To examine the transfer system, apply the loop formulas:
(Equation 1)
(Equation 2)
(Equation 3)
It follows that the overall transfer function for the CLG of the PLL equates to:
(Equation 4)
(Equation 5)
(Equation 6)
So, the transfer function depends on KD, KV, Z(s), and N. Designing the loop filter means using the transfer function. A variation in any of the transfer-function components will affect the loop response. The next topic to examine is why the wideband VCO has a KV that is nonlinear and what can be done to compensate for this.
Wideband-VCO KV
KV is mainly affected by the capacitance-versus-voltage (CV) characteristic of the on-chip varactor. In most narrowband PLL applications, the VCO KV is more or less a constant value. This is due to the varactor of the VCO only being used in a narrow region of bandwidth. Wideband VCOs, however, exercise the varactor CV characteristic over a much wider tuning range. Different VCO manufacturers employ different techniques to attain a wide bandwidth, while using just one varactor. The trade-off for this wide bandwidth is that the KV of the VCO will suffer as the internal circuitry tries to compensate for a varactor with a CV characteristic curve that is working against it.
Figure 2 shows a KV graph of the Micro-netics M3500-2235 wideband VCO that was used as the VCO in the example PLL circuit. There are two lines plotted on the graph. The blue is the datasheet plot, and the red is the plot of the actual VCO used. As can be seen in the graph, the measured sensitivity ranges from 22 MHz/V to 110 MHz/V across the tuning range.
This nonlinearity is not a characteristic of the particular VCO, but of the way that wideband VCO architectures are implemented. The effect of KV on the open- and closed-loop filter response was previously examined, so it can be seen that for the wideband PLL in question we can expect a variation in CLB.
Example circuit
The objective is to design a PLL circuit that will minimize the nonlinear KV introduced by the wideband VCO. The synthesizer used in the example has a programmable charge pump with eight different settings that will be used to ensure that the loop stability is maintained. It also has a maximum operating frequency of 4 GHz. This gives a comfortable margin above the 3.7-GHz maximum output that the Micronetics VCO works up to. For the circuit design, and the loop-filter design in particular, some assumptions have to be made.
At first, an attempt will be made to design a ‘best fit’ filter. The filter response will be analyzed at the highest, lowest, and middle values of VCO KV to gauge the effects of the VCO on the loop. The average measured VCO KV (84 MHz/V) will be used. Other assumptions are that the synthesizer charge-pump current is set at 2.5mA and that the loop specification requires a 1-MHz channel space, a CLB response of 40 kHz, and a phase margin of 45 degrees.
A VCO output frequency of 3.28 GHz (which corresponds to a KV of 84 MHz/V) is chosen. Since the circuit has an operational-amplifier (op-amp) gain of 4 in the loop, this will contribute a current gain of 4, which must also be taken into account. This best fit filter attempts to maintain loop stability for as wide a tuning range as possible. At the very least it should exhibit a stable 40-kHz filter response at 3.28 GHz. Figure 3 is a circuit diagram for the wideband PLL used.
The next thing to investigate is what the filter CLBW response looks like across the frequency band of the PLL. The results concentrate on the extremities of KV. Figure 4a shows the filter response for the PLL at the lowest, highest, and average KV across the entire band from 2.2 to 3.7 GHz. The extremes of VCO sensitivity correspond to 2.625 GHz (110 MHz/V) and 3.66 GHz (22 MHz/V). The filter certainly behaves at the designed frequency of 3.28 GHz, with a CLBW of 42 kHz. But the closed-loop bandwidth response at the extremities varies from 15 kHz at 2.625 GHz to 90 kHz at 3.66 GHz.
The solution
It has now been shown in theory and in practice how, if the KV varies, it will effect the transfer function, and hence the filter will behave nonideally, leading to a large and possibly unacceptable variation in CLBW. The theory earlier suggests that dynamically varying another loop parameter to negate the effect of the nonlinear KV could ensure loop stability. This is where the idea of changing the charge-pump current to compensate for the nonlinear KV comes from.
The KV and the ICP exhibit a direct proportional effect on loop stability. To negate a loop with a large KV, reduce ICP, and vice versa. The frequency synthesizer used has a programmable charge pump with eight settings. These range from 0.625 to 5mA in 0.625-mA steps (when an external RSET resistor of 4.7k is used with the device). By breaking the VCO KV plot into eight segments, it is possible to create Table 1, which shows the ICP to choose for a particular KV to act as the compensation factor.
Figure 4b shows the closed- loop bandwidth variation across the entire VCO tuning range after dynamic current compensation. The results show that the closed-loop bandwidth varies only from 30 to 42 kHz. When compared to the uncompensated result, the dynamic current compensation shows its worth.
Stability
At this point, further study into loop stability yields interesting results. Control theory definitions are necessary before proceeding. As described earlier, instability is defined as having an open-loop phase of 180 degrees at the open-loop unity gain frequency. Phase margin is the measure of open-loop phase. The example PLL was designed to attain a phase margin of 45 degrees (a typical phase margin for a PLL system). A quick and easy way to determine loop stability is to look at the shape of the inband filter response. Instability manifests itself as the peak in the rise of the inband filter response. The rule is simple: the higher the peak, the more unstable the system. For the 2.625-GHz case (uncompensated), there is approximately 7-dB peaking in the filter response, and as much as 10-dB peaking in the 3.66-GHz case (uncompensated). Obviously, a more in-depth study into this is needed.
Simulations were carried out to quantify the phase-margin variation in the example circuit. They show that this uncompensated filter features a phase margin varying from 38 (2.625 GHz) to 44 degrees (3.28 GHz) and back to 33 degrees (3.66 GHz). These results stack up with the peaking observation method above. Further simulations on the compensated circuit result in a phase-margin variation from 43.2 to 45.5 degrees. This is a factor of five improvement in phase-margin variation. Stability variation also has other effects on loop design. One is that the peak of the inband filter response introduces an increase in integrated phase noise of the PLL.
Loop settling
Settling time is directly related to the filter response of a PLL. Variations in KV will affect the loop transfer function and hence loop settling time. The uncompensated results lead to a loop settling time variation of up to a factor of six. The loop settling time for the average case (3.28 GHz) is 270 µs, while the extremes of the PLL show a variation from 130 µs (3.66 GHz) to 770 µs (2.625 GHz). When the compensated PLL is examined, there is a reduction to a worst-case settling-time variation of less than 100 µs (230 to 300 µs).
Phase noise is another critical, if not the most critical, specification when designing a PLL. The basis behind all communications systems is bit-error rate (BER). Integrated phase noise of the synthesizer contributes to the root-mean-square (RMS) phase error of the transceiver. Therefore, any variation in synthesizer integrated phase noise will affect the entire transceiver BER performance. This all boils down to the need for the local oscillator (LO) to exhibit excellent phase-noise performance.
Figure 5 shows a phase-noise plot of the example circuit. The phase-noise performance of –85.5 dBc/Hz at 1-kHz offset equates to a phase frequency detector (PFD) noise floor of –156 dBc/Hz. Transceiver designers work to integrate phase-noise specifications. Any variations in filter response will lead to a variation in phase-noise performance. The uncompensated circuit has a worst-case variation in integrated phase noise of 0.9 degrees. Compensated, this variation is reduced to 0.2 degrees.
The amplitude of reference spurious signals is another factor that is affected by loop-filter dynamics. Although there aren’t any reference spurs appearing above the noise floor of the PLL, by examining Figure 4a and Figure 4b, intuitive comments can be made about the reference spurs that would be present in the circuit. For the system with a 1-MHz PFD frequency, reference spurs will be present at 1-MHz offset from the carrier. Concentrating on Figure 4a, it can be seen that at 1-MHz frequency offset, any reference spurs present would vary in amplitude by approximately 15 dB across the entire VCO bandwidth.
Again, this is due to the variation in filter response resulting from the nonlinear KV of the wideband VCO. In Figure 4b, this reference spur amplitude variation across the bandwidth is reduced to approximately 7dB by the charge-pump current compensation. As can be seen in Figures 4a and 4b, the reference spurs in the example circuit are actually below the noise floor. This is due to the attenuation provided by the loop filter and also the synthesizer phase-frequency detector and charge pump having excellent spur performance.
This design idea is not just restricted to wideband VCOs. There are many narrowband VCOs that also exhibit nonlinear KV.
It has been shown that if the charge pump of the frequency synthesizer is flexible enough, it can compensate for the variations in KV that are inherent in wideband VCOs. This ensures that the loop response is more predictable and also that a more stable PLL results. Employing dynamic compensation prevents a wide variation in CLBW, stability, settling time, and integrated phase noise, each of which is an essential element in PLL design.
Acknowledgements
The author would like to thank Mike Curtin, Mike Tuthill, Paul O’Brien, and Adrian Fox of Analog Devices for their help in researching this article.
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