|
Carrier Synchronization Techniques For DSP-Based Modems
By Fred Harris
As DSP-based modem designs quickly emerge, system designers will begin to encounter problems extracting information from received signals. Through the use of synchronization techniques, designers can obtain the carrier and timing information needed to better develop their system designs.
As developers continue to request digital modem technology, there has been a quick move toward DSP-based modem designs. In these designs, data is moved through a communication channel using a modulator at the transmitter to apply a succession of transformations to a binary data stream. The demodulator at the receiver then inverts these transformations to form estimates of the data stream that was originally presented to the modulator.
Although DSP-based modem designs offer key benefits to designers, there are several considerations that designers encounter when implementing these modem solutions. In particular, DSP-based modem technologies may not include pilot and training signals. Therefore, the demodulator must extract the carrier and timing information from the received signals based on secondary signal properties related to excess bandwidth and state-transition activity. This article will review the process of extracting carrier information from received signals in a DSP-based modem design.
The modulated signal
A modulated signal may be described in the following manner. In response to information symbols Ik delivered periodically at time increments of Tk, a modulator forms a signal as a spectrally translated weighted sum of shaped time functions. The amplitudes of the information symbols and the waveform g(t) are complex so that the time signal is amplitude and phase modulated. This signal is shown in Equation 1a and Equation 1b
(Equation 1a)
 (Equation 1b)
The signal received from the channel arrives with unknown amplitude, time delay, frequency shift, phase shift, and additive noise. This is shown in Equation 2.
 (Equation 2)
Assume that the unknown channel attenuation, A(t), varies slowly with respect to the modulation signal and is removed by an automatic-gain control (AGC) loop. If A(t) introduces frequency-dependent distortion, an equalizer must to process the received signal. A designer can assume that the time scales of the channel effects are widely separated and that the loop time constants are appropriately selected. Under this condition, a designer can ignore any interaction between the many loops. Thus, the tasks addressed here include estimating and removing the effects of frequency and phase offsets. The signal delivered to the demodulator can be described as a known signal with these parameters (Dv, DU, and, Dt) of unknown value, as shown in Equation 3.
 (Equation 3)
The parameters highlighted in Equation 3 can be estimated independently in a specified order; can be estimated with aid from previous estimators in the sequential chain; or can be estimated concurrently but independently, or concurrently and cooperatively. The most common practice is concurrent-independent acquisition or concurrent-aided acquisition. Another common practice involves switching between modes, initializing unaided, and then operating aided to improve noise immunity.
Carrier-frequency offset and carrier-phase acquisition are often treated as sequential tasks. Carrier-frequency offset must be resolved prior to acquiring phase offset since sizeable carrier offsets will prevent successful acquisition of the phase
by the phase-locked loop (PLL). Similarly, a severely distorted wave shape may defeat the acquisition of the timing parameters by the timing-recovery PLL. A sizeable frequency offset may place the input signal bandwidth in the frequency band rejected by the receiver's passband filters.
The passband filter rejects part of the input bandwidth of the frequency-offset signal. The spectral distortion will distort the received time signal. Thus, if the receiver must accommodate a significant amount of center frequency offset, the receiver's passband bandwidth must be increased. Unfortunately, this increases the receiver's noise bandwidth and susceptibility to adjacent-channel signals.
Frequency estimation
There are a number of algorithms a designer can apply to the input signal to estimate the offset frequency or to indicate the presence and direction of a significant offset. This article only examines algorithms that work independently of decision information.
The first option is a channelized bank of matched filters that span the expected range of frequency offset. The difference in center frequencies of the filter bank is selected to be less than the lock range of the PLL. The more traditional and less expensive implementation sequentially synthesizes the bank of matched filters with a single downconverter and matched filter that is time shared across the frequency-offset search range by applying an FM sweep
to the local digital oscillator. The sweep is terminated and held when the energy detector declares a detected peak. The disadvantage
of the scanning approach is the increased time required to acquire
a lock.
A second option for estimating frequency offset is to employ a Fast Fourier transform (FFT) that interrogates the entire frequency span collected by the input time-sampling process. The time series is first windowed to minimize boundary-related artifacts, transformed, and then converted to power. A combination of FFT and successive block-spectral shifts may be used to span the entire bandwidth of the input signal.
The process of forming spectral estimates from each synthesized filter is repeated for successive overlapped time intervals and averaged to obtain stable (low-variance) estimates of their relative energy content. The ensemble of averaged spectral terms is compared to determine the filter with the maximum output energy. The center frequency corresponding to the peak is the frequency to which the digital downconverter should be tuned for coarse translation prior to the carrier-phase PLL.
The advantage of this processing option is that the parallel search of the spectral region can be conducted at low cost and with little resource allocation. This is due to the exceptional computational efficiency with which the FFT makes available the raw spectral estimates required to synthesize the filter banks.
Direct measure of offset
Frequency shift of an offset baseband signal can be determined directly by estimating the rotation rate, DvT = Du, of the complex phasors. Samples of the complex baseband signal are of the form shown in Equation 4.
(Equation 4)
A designer can form the conjugate product of the signal and a one-sample-delayed version of the signal as seen in Equations 5a through 5c.
(Equation 5a)
(Equation 5b)
(Equation 5c)
Note that this conjugate cross product has an argument containing the rate of rotation and the phase difference of successive samples
of the modulation envelope. The expected value of the argument of Equation 5c is an unbiased estimate of the residual frequency offset.
Successive samples of the complex envelope are correlated and the expected value of the complex envelope will be non-zero. The average formed across many samples of the cross product is required to reduce the variance of the estimate due to data modulation and additive noise. Thus, an estimate
of the frequency offset can be obtained as shown in Equation 6.
(Equation 6)
In this equation, the phase-rotation estimate can be used to steer the direct digital synthesizer (DDS) of the carrier-phase PLL to the correct frequency offset or it can used as part of the feedback loop as a frequency-lock contribution to the phase error of the loop.
The final indicator of frequency offset is obtained from band-edge filters, sometimes known as frequency-matched filters. These filters have a frequency response equal to the product of the matched filter times the frequency-domain derivative of the matched filter. A Hilbert transform separates the positive and negative frequencies of the band-edge filter.
An input signal presented to the band-edge filter will contribute energy to each of the two filters. If the spectrum of the input signal is centered at zero frequency, the energy contributed to each filter is the same. On the other hand, if the spectrum of the input signal is shifted from zero, for example to the left, the left filter will collect additional energy while the right filter will collect less. The difference in energy content of the two band-edge filters is proportional to the frequency offset of the input spectrum.
Squaring
The task of phase locking to a carrier delivering the modulated signal to the receiver presents an interesting problem to a designer. In many communication systems there is not any copy of the carrier accompanying the modulated signal. Some systems do insert a carrier or a pilot carrier to which a PLL can lock. For these systems it's simply a matter of reducing the bandwidth around the spectral line to minimize the self-noise (sometimes called modulation noise) contributed by the random modulation.
For systems without a carrier, the signal must be subjected to a nonlinearity to form a spectral line that the PLL can lock on to. The nonlinearity is normally one or more multipliers or decision devices operating as phase detectors.
The task of obtaining a phase-locked replica of the carrier associated with a double sideband suppressed-carrier (DSB-SC) modulated signal must also be considered. Binary phase shift keying (BPSK) is a digital modulation that fits in this category. The form of the received signal plus noise is shown in Equation 7. The probability density function P(A) is arbitrary with zero mean, and the phase f is similarly arbitrary as well as slowly changing with time as shown in Equation 7.
(Equation 7)
The signal does not have a spectral line at the carrier frequency since the amplitude A(t) is zero mean. A designer forms spectral lines by squaring the signal. The squaring operation generates a spectral line at DC at twice the carrier frequency and at three cross terms. These cross terms are signal times signal, noise times noise, and signal times noise. The terms are shown in Equations 8a and 8b.
(Equation 8)
(Equation 8b)
Examining the terms in Equation 8b, a designer can conclude that A2(t) and n2(t) feature non-zero means that form the spectral lines at DC and at 2vc. Furthermore, the convolutions of the bandwidth of A(t) with A(t), of n(t) with n(t), and of A(t) with n(t) form spectral masses centered about the DC line and the 2vc line.
The spectra of a BPSK signal and the squared version of that signal are shown in Figure 1. The simulation that generated these figures had a center frequency 10% of sample rate and the symbol rate 1/16 of the sample rate. Notice that the input spectrum does not have any spectral lines and that the squared signal spectrum has smeared spectral mass and lines at DC as well as at 20% of the sample rate. Also note the additional spectral lines at the symbol rate.
The structure of a squaring loop is shown in Figure 2, where the squaring operation generates a double frequency line. To obtain the appropriate signal carrier required for the desired downconversion operation, a designer must divide the frequency of this line by a factor of two. A designer can accomplish this task with a frequency doubler inside the PLL loop and extract the desired mixing term at the input to the doubler.
Squaring-loop problems
The squaring loop will work with any BPSK modulation scheme because the doubling of the phase argument due to the squaring operation maps the two input phase angles to the same output angle (2 times 0, and 2 times p). A problem with the squaring loop, however, is the extra noise terms resulting from the cross product between signal and noise. This cross term introduces up to a 3-dB reduction in SNR that is termed the squaring loss.
The squaring loop also has a phase ambiguity of p since two phase angles map to the same output phase. The amplitude (+1)2 is indistinguishable from the amplitude (ý1)2. This phase ambiguity is resolved in the demodulation process or is suppressed by using differential BPSK modulation.
Costas-loop estimations
To understand Costas loop estimations for BPSK communication systems, assume that the transmitted signal is of the form shown in Equation 9, with the signal amplitude just as likely to be ýA.
 (Equation 9)
The likelihood function is the conditional density function for known signals with unknown parameters in additive white Gaussian noise (AWGN). Maximum-likelihood estimators seek values of the unknown parameters that maximize the density function. This is equivalent to minimizing the width of the density function about the mean value.
The likelihood function for the received BPSK signal in noise, averaged over the density of input amplitudes, is shown in Equation 10a and 10b. In this equation, r(t) is the received signal with unknown phase, cos(vct+f) is the test function being adjusted to maximize the likelihood function, and N0/2 is the power-spectral density of the additive noise.
(Equation 10a)
(Equation 10b)
Since the exponential function
is monotonic, maximizing the likelihood function is the same as maximizing the log-likelihood function, a maneuver often used to eliminate the exponential in the likelihood function. The log-likelihood function is shown in Equation 11.
 (Equation 11)
The function ln[cosh(x)] can be approximated in two regions of its argument. The approximating regions can be computed using Equation 11a.
 (Equation 11a
For small values of the argument, meaning a small signal-to-noise-ratio (SNR), Equation 11 can be approximated by the function shown in Equation 12.
 (Equation 12)
A designer can then differentiate Equation 12 with respect to f and set to zero to obtain Equation 13.
 (Equation 13)
Equation 13 instructs the designer to heterodyne the received signal r(t) with quadrature versions of the local oscillator (LO), average these signals over a symbol duration, and adjust the phase angle f until the product of the two arms is zero.
For a large SNR ratio, Equation 13 can be approximated using Equation 14. A designer can then differentiate Equation 14 with respect to f and set to zero to obtain Equation 15.
(Equation 14)
(Equation 15)
Equation 15 instructs the designer to heterodyne the received signal r(t) with quadrature versions of the LO, average these signals across a symbol duration, and adjust the phase angle f until the product of the sine arm with the sign of the cos arm is zero.
Examining the Costas loop
The next step is to examine the Costas loop for carrier acquisition of DSB-SC. A block diagram of the Costas loop is shown in Figure 3.
The Costas loop averages
over the entire symbol interval as opposed to responding to the peak value of the symbol interval determined by the time-synchronized sample. The Costas loop is an approximation to the small SNR model of the maximum likelihood (ML) phase estimator. A designer can examine the equations of the Costas loop to determine the behavior of the phase-error term. As described earlier, one can assume that the received signal is of the form shown in Equation 16.
 (Equation 16)
The product formed in the upper arm of the Costas loop is shown in Equation 17. The prod-uct formed in the lower arm of the Costas loop is shown in Equation 18. The product formed at the phase detector on the right is shown in Equation 19. Finally, the approximate output of the loop filter is the term presented in Equation 20.
(Equation 16)
(Equation 17)
(Equation 18)
(Equation 19)
(Equation 20)
Since the loop is averaged over the entire interval, designers must examine the phase response of the phase detector feeding error signals to the loop filter. By doing this, de-signers will gain insight about the Costas loop, which will permit them to compare the Costas loop with the ML estimator. Additionally, by examining the phase response of the detector, designers will gain clues to its use with a quadrature amplitude modulation (QAM) signal.
Phase detectors
When examining the phase detector, a designer can consider in-phase (I) and quadrature (Q) components of the complex downconverter as points in two-dimensional (2D) signal space. These points define angles that eventually drive the loop through the amplitude-sensitive gain proportional to average signal energy (see Equation 20). The components in the I & Q legs of the Costas loop can be considered (A/2)cos(Df) and (A/2)sin(Df), respectively. The phase detector forms the product of these terms. A designer can examine the transfer function of the detector by studying the product as a function of Df. Figure 4 presents this curve as a function of normalized phase (Df/2p).
In Figure 4, it is important to note that for small angles, near 0 and 0.5, the phase detector presents a gain proportional to Df. The loop can lock equally well at either phase angle. This is the same ambiguity observed in the squaring loop. The phase response observed here is the same as that derived for the ML estimator operating with a small SNR. The difference in the two systems is the proportionality factor. In this case, phase response is the average energy in the symbol, while in the ML estimator it is the peak energy obtained from the output of the matched filter.
The next logical question to ask is what the phase detector transfer function would look like if the large-SNR model is used. If the large SNR model is used, a designer must multiply the sign of the cosine leg with the output of the sine leg.
As before, the detector response repeats at 0 and 0.5, and thus will lock at either phase point. A designer should also notice that the gain is higher, is more linear, and does not have a negative slope in its operating range. A designer should expect higher gains when the signal exhibits higher SNR. Similarly, a designer should not have high confidence in the sign operator applied to the I arm in cases of low SNR.
Recognizing the structure
The designer is now in a position to recognize the structure that the phase detector must exhibit to successfully support phase lock to a QAM or QPSK signal. The structure must exhibit a four-fold symmetry about the four possible phase angles of the input signal. The clue for this structure is found in the cross product of the high-SNR phase detector in the ML estimator, Q* sign(I). The system, which forms the four-fold symmetry, follows Equation 21.
(Equation 21)
This phase detector exhibits the expected four-fold symmetry about the angles corresponding to the odd multiples of p/4. Other phase detectors can be formed for other constellation sets. These detectors are normally connected to the input and output ports of an I & Q quantizer.
This article is based on a presentation made at the DSPWorld Spring Conference in San Jose, CA. www.dspworld.com.
Author's Note
A synchronous receiver must acquire phase and frequency of an input carrier to successfully demodulate the complex waveform imposed on that carrier. It must often accomplish this feat without assistance from the transmitter. The process of obtaining phase lock is well-understood and well-documented in many excellent texts. This article addressed just one part of the required tool set. The full complement of tools includes, besides this material, an understanding of PLLs and of timing recovery mechanisms. In addition, more than a nodding acquaintance with DSP techniques in modern communication systems is required. Look at the bibliography containing material on the PLL, timing, and carrier-recovery techniques.
| 
Puzzled by a network processing design issue?
