CSD June 2000 Code Listings: Bringing Parallel Processing to FPGA Designs

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15 March 2010

Code Listings: Bringing Parallel Processing to FPGA Designs

Code Listing 2

ECU ECU0(.Clock(clk), Reset(rst), .XBus(r0),
.YBus(c0), .AdderBus(), .Cin(), .IBus(ibus), .Sign(sign),
.Result(res_ecu0), .Cout(cout_ecu0));
ECU ECU1(.Clock(clk), Reset(rst), .XBus(r1), .YBus(c1),
.AdderBus(res_ecu0), .Cin(cin0), .IBus(ibus),
.Sign(sign), .Result(res_ecu1), .Cout(cout_ecu1));
.
.
.
ECU ECU7(.Clock(clk), Reset(rst), .XBus(r7), .YBus(c7),
.AdderBus(res_ecu6), .Cin(cin6), .IBus(ibus),
.Sign(sign), .Result(filter_output), .Cout(filter_cout));

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