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18 March 2010

Code Listings: Bringing Parallel Processing to FPGA Designs

Code Listing 1


Module ECU(Clock, Reset, XBus, YBus, AdderBus, Cin, IBus, Sign, Result, Cout);
Input Clock, Reset;
Input [7:0] XBus, YBus; // multiplier intputs
Input [15:0] AdderBus; // adder inputs
Input Sign; // sign bit used for sign or unsigned arithmetic
Output [15:0] Result; // output bus
Output Cout;
// ECU model info from ESP vendor found here
Endmodule
// Up to 18 different data paths can be created thus 18 separate ECU modules can be instantiated as shown below
ECU ECU0(.Clock(clk), Reset(rst), .XBus(xbus0), .YBus(ybus0), .AdderBus(adder0),
.Cin(cin0), .IBus(ibus0), .Sign(sign_0), .Result(res_ecu0), .Cout(cout_ecu0));
ECU ECU1(.Clock(clk), Reset(rst), .XBus(xbus1), .YBus(ybus1), .AdderBus(adder1),
.Cin(cin1), .IBus(ibus1), .Sign(sign_1), .Result(res_ecu1), .Cout(cout_ecu1));
.
.
.
ECU ECU17(.Clock(clk), Reset(rst), .XBus(xbus17), .YBus(ybus17), .AdderBus(adder17),
.Cin(cin17), .IBus(ibus17), .Sign(sign_17), .Result(res_ecu17), .Cout(cout_ecu17));

Return to the Feature: Bringing Parallel Processing to FPGA Designs
Return to the SOC Special Section




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