Special Section

This section will provide a glimpse of some hot design issues associated with developing SOCs for communication designs. Specifically, this section highlights SOC issues found in field-programmable gate array (FPGA) designs. Additionally, the section details several interconnect architecture decisions engineers need to make when choosing SOC ICs.

For the last few years, the SOC has been the Holy Grail of the communication design community. Designers across the industry are searching for ICs that combine the functionality of an entire system onto a single piece of silicon. Although we have yet to see full systems on chips, the reality is that SOC ICs are already playing a large part in the communication design process. Base-band processors are combining the functionality of DSPs and microcontrollers on a chip. FPGAs are linking multiple blocks on single pieces of silicon. Mixed-signal and digital functionality are coming together on ASICs. The list goes on.

As designers well know, SOCs come in a variety of flavors and are found in numerous market segments. One market segment that has embraced the SOC mentality is the FPGA sector. Communication Systems Design's SOC Special Section will highlight the technologies needed to link embedded arithmetic units with traditional FPGA functionality. By doing this, the section will demonstrate how parallel processing capabilities can be offered in FPGA devices.

Designers also know that in any SOC IC, it is crucial to efficiently link multiple intellectual property (IP) blocks together. In order to do this, engineers need good interconnect architectures. This month's SOC supplement explores four interconnection architectures engineers can employ in an SOC, weighing the benefits and drawbacks of each approach.

–Rob Keenan
rkeenan@cmp.com