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Flash Memory Choices for Portable Designs
By Doug Wong
Since portable communication systems continue to house more functionality, Flash memory is becoming a bigger
concern for system designers. As designs continue to evolve, new Flash architectures are being developed to address the specific engineering requirements of these systems.
Today’s portable systems designers, such as cell phone and PDA developers, are faced with a bewildering array of choices: different microprocessors, memory subsystems, and I/O devices. The optimal choice depends on a large number of constraints: time-to-market, cost, engineering effort, size, power, weight, and performance,
just to name a few. Since every project will assign different importance to each of these constraints, the best solution differs from project to project.
All electronic systems running algorithms are essentially sophisticated finite state machines. The processor can be thought of as a complicated next-state decoder, while the memory holds the current state of the machine (which acts as the register in a classic Mealy or Moore finite state machine). At power up, the state of the system must be
initialized from nonvolatile memory as well as all defined next-state transitions (the algorithm or program code). Thus, Flash memory is essential for portable communication designs for storage of programmable code.
System architectures
There are a number of Flash memory devices currently available in the market, giving system designers a plethora of choices. The best choice really
depends on the system architecture chosen.
There are three basic system architectures in use for today’s portable communication devices. These architectures include the PC model, the small microprocessor model, and the medium microprocessor model.
In a typical PC model, the processor initially boots from the basic I/O system (BIOS) stored in Flash memory. The BIOS is next copied (shadowed) into DRAM for faster execution. The operating system (OS) is then loaded from the hard disk drive
into DRAM. Finally, user applications are loaded into DRAM for execution.
The PC model is characterized by three properties. First, this model is saddled with a slow boot process. Although versatile, this process has gotten slower as the OSes have gotten more sophisticated. For PCs to become more consumer-friendly, this process needs to be shortened. No consumer would tolerate any tele-vision that takes as long to turn on as a PC.
The PC model also delivers high-speed execution from DRAM.
Copying all code into RAM offers the best possible performance, but contributes to the slow boot process. A large amount of DRAM is necessary to hold both the OS and the applications. Graceful power down is also difficult to achieve, because it is necessary to copy the state of the machine to nonvolatile memory or the hard disk drive.
Finally, the PC model is power intensive. DRAM is designed to meet the needs of the PC market, not for minimal power consumption
The PC architecture uses little
Flash memory because the nonvolatile storage of the system is a physical hard disk drive. Although the architecture offers the best performance, it is difficult to migrate the architecture to smaller systems, especially portable, battery-operated information appliances due to power, weight, and usability considerations (leading to an unacceptably slow startup time).
Small model
For small, embedded microprocessor systems, programs are typically executed directly from nonvolatile memory. External system RAM, if it exists, is often in the form of SRAM because the required amount of RAM is limited, no shadowing of code into RAM is required, a DRAM controller is not built-in, and the SRAM offers lower standby power characteristics — important for battery-powered systems. For these systems, Flash memory has replaced EPROM as the nonvolatile memory of choice.
Systems employing small microprocessors generally offer boot code/OS/application code executed directly from the Flash. A random access interface is required, so only NOR-type Flash (sometimes referred to as eXecute In Place [XIP]) is applicable.
Small microprocessor systems are also characterized by low power operation and lower speed operation. On the speed side, DRAM has significantly faster read cycles than Flash at the present time, so systems executing code directly from Flash cannot yet achieve
the same performance.
Many consumer products such as digital cellular phones and cable set-top boxes employ the small microprocessor architecture. Top performance is not yet required, so the relatively slow read performance of NOR Flash compared to DRAM is not a bottleneck on overall system performance.
Medium Model
The final architecture for portable communication
devices is the medium microprocessor model. Portable systems employing this architecture have adopted a hybrid approach. For performance reasons, these systems, which may house Internet browsers and the Windows CE OS, require large amounts of DRAM. At the same time, these systems employ Flash memory as nonvolatile memory, storing the OS and application, and as the solid-state drive for holding data.
In medium microprocessor-based systems, system boots are performed from a small density NOR Flash.
Additionally, the OS and application are copied from mass storage Flash, while data is stored in the mass storage Flash. Finally, applications on these systems are executed from system RAM.
Flash memory types
The first Flash devices were derived from EPROMs, which have a random, direct access interface. By emerging from the EPROMworld, the first Flash devices offered a direct connection
with the microprocessor bus and were compatible with microprocessor read and write cycles. This type of Flash is known as Not OR (NOR)-type Flash.
Today, there are two basic Flash memory cell architectures: NOR and Not AND (NAND). The memory storage transistor is basically the same for both, consisting of a control line, a polysilicon line surrounded by an insulating oxide (known as a floating gate), and source and drain regions of the transistor itself. It is the interconnection of these memory
cells that differentiates the designs.
The simplified NOR cell architecture derives its name from its resemblance to NOR logic (see
Figure 1
). In a NOR gate, the output is 0 if any of the inputs are 1. Analogously, in the NOR Flash memory array, the bit line goes to 0 if any of the memory cell transistors turn on. The NOR architecture consists of a parallel connection of memory cell transistors to a bit line.
The simplified NAND cell architecture
derives its name from the resemblance to a NAND logic gate (as shown in
Figure 2
). In a NAND gate, the output goes to 0 if all of the inputs are 1. In a NAND Flash memory array, the bit lines go to 0 if all the memory cell transistors turn on. The NAND architecture is a series connection of memory cell transistors to the bit line.
Each Flash memory architecture has its own distinct advantages. The NOR architecture has fast random read speeds, but slow erase
and write speeds. The high read speeds make the NOR architecture suitable for fast random access such as that required for program execution. Therefore, similar to EPROMs, the interface to NOR Flash memory is designed for direct memory access: separate address, data, and control lines. This enables a direct connection to microprocessors and permits direct execution of program code.
The NAND architecture has a relatively slow random read speed (because the series connection of transistors reduces the
cell current) but fast erase and program speeds. Due to the slow internal read speed, the device was designed to transfer entire “pages” of data at a time. Data is transferred between the memory array and an internal data register in 528-byte units. Then, data is transferred one byte at a time between this internal data register and an external 8-bit bus. The average read speed is comparable to NOR Flash if whole sectors of data are read out.
Due to the series connection of the memory
cells, the NAND Flash memory array is the smallest Flash memory type, enabling minimum silicon die to store a given number of bits. NAND Flash is designed primarily for solid-state file storage. The interface is indirect; there are no dedicated address or data lines, just control lines and an 8-bit I/O port. Future densities will have the same number of pins as previous densities. Like the IDE interface on hard disk drives, the indirect interface of NAND Flash allows the use of the same physical connections
with future generations of NAND (see
Table 1
).
Because of the higher program and erase speed and smaller die size, NAND Flash is the best solution for systems requiring mass storage.
Future architectures
Although fundamental Flash architectures may not change dramatically, Flash technology continues to evolve at a rapid pace.
Foremost among the changes is the rapid shrinkage of minimum feature size, or design rules. The latest Flash devices from major manufacturers now feature minimum line widths less than 0.3 mm. This scaling will continue to allow per-bit prices to drop (as chip sizes decrease) while densities increase.
To maintain constant electric field levels inside the chip, the nominal operating voltages need to decrease. This decrease in internal voltage may be hidden from the communication systems designer because of
on-chip voltage translators, but internally, the device will operate at a lower voltage. Many systems will actually benefit from the decreased supply voltage requirements, especially battery-operated devices such as digital cellular phones and advanced messaging devices.
In nearly all memory devices (DRAMs, SRAMs, MROMs, EEPROMs, and Flash), each memory cell typically stores 1 bit of information, a 1 or a 0. For example, in a 16-Mbit Flash device, the memory array is composed of 16 million
transistors. In these devices, a single threshold level separates the 0 state from the 1 state. In Flash memory, these two states are differentiated by the amount of charge on the floating gate of a memory cell transistor. If one could accurately control the amount of charge so that four charge states were distinguishable, then 2 bits of information could be stored in a single transistor, thereby halving the number of memory transistors required. If eight states are distinguishable, then 3 bits of information can
be stored per memory cell transistor.
Experimentally researched for many years, several manufacturers have introduced multilevel cell (MLC) devices (see
Figure 3
). MLC technology promises a significantly reduced cost per bit, but it may turn out to be less effective than expected. Ultimately, chip cost is related to die yield and die area. Since the die area consists of peripheral circuitry, control circuitry, and memory array area, halving the memory
array using a 2-bit MLC design will not halve the die area.
For applications that are very sensitive to cost per bit, MLC Flash may be the most cost-effective approach. However, there are trade-offs. Data shows that MLC designs have three to four times longer programming times and lower write/erase cycle endurance. Although the block-erase and read times are expected to be comparable to single-bit per-cell Flash, the longer programming time and reduced lifetime may make MLC Flash less desirable for
solid state disk drives than standard single-bit per-cell Flash.
Specialized Devices
As Flash technology matures, the development of specialized Flash devices optimized for specific functionality is inevitable. While NAND Flash is optimized for use as a solid-state drive, improvements in NOR Flash are on the horizon.
One improvement popping up is the development of
read-while-write (RWW) NOR Flash products, which are essentially two or more Flash memory arrays on a die. This enables the user to read from one array while programming or erasing the other array. RWW NOR Flash has enabled cellular phone manufacturers to eliminate a separate EEPROM chip from phones that used to store telephone numbers, names, and other data. Since it is similar to having two Flash chips in the same package, one array can be used to store data, while code is executed from the other array.
The next development in NOR Flash memory will likely address the need for increased performance. Random access speeds will continue to decrease as lithography decreases, but the falling supply voltage could work against this. The next evolutionary step is likely to be the emergence of synchronous Flash devices. Both SRAMs and DRAMs used to be asynchronous (without a clock signal) until it became impossible to squeeze timing margins any further. Today, the very fastest SRAMs and DRAMs are synchronous, and
it is just a matter of time before Flash follows suit.
For systems whose architecture is similar to the PC model or the medium microprocessor model, a long boot time is a necessary consequence. Yet, much of the data in system RAM is static, either being OS code or application code. Anecdotal evidence suggests that 70% of the data in RAM is static code and not variable storage or data. Replacing 70% of the system RAM with synchronous Flash having the same speed as SDRAM, would save both cost and
power. In addition, the boot-up time might be reduced to an instant since there would be no need to copy code from a hard disk drive or mass storage device into RAM. Instant power management might become possible. There is no reason for a system to be running at full speed while waiting for the user to do something; idling a system in between user events could achieve significant power savings.
The new portable communication applications, which employ small microprocessor architectures, are driving
the need for improvements in Flash memory. As communication technology continues to proliferate, there is a clear demand by end users to stay connected and get information anywhere, anytime. This will drive the development of ever more sophisticated cellular phones with more built-in features like voice-recognition and built-in video. Will a PDA and a cellular phone morph into one unit? Perhaps, but no one wants to use an unwieldy hybrid that does everything, but does it poorly. Battery life will be a key
parameter for these types of applications.
The key to next-generation portable communication devices, also dubbed information appliances, is to harness the ever increasing amounts of processing power and make complicated operations simple for the end-user. This will require intelligent software, all stored on the next generations of Flash memory.
Here to stay
Flash memory
is one of the key memory technologies of today’s systems. NOR Flash has succeeded in replacing EPROM as the main non-volatile memory of choice, while NAND Flash has become the popular choice for solid-state mass storage. Until the ideal memory combining the best features of both RAM and ROM is developed and commercially viable in mass production, Flash memory will continue to improve and differentiate to meet the needs of the market.
Doug Wong
is a member of the technical
staff for the memory business unit at Toshiba America Electronic Components, Inc. He received a BSEE from California Polytechnic State University at San Luis Obispo and an MSEE from the University of California at Los Angeles. He can be reached at
doug.wong@taec.toshiba.com.
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