Lessons in Designing LEOs: Part 1 - Tables

TABLE 1: Example Scheduler Input Matrix
	Output port 1	Output port 2	Output port 3
Input port 1	3	0	1
Input port 2	0	0	1
Input port 3	2	1	None

TABLE 2: Example Round 1 Score
	Output port 1	Output port 2	Output port 3
Input port 1	321111	022012	111231
Input port 2	021121	032022	122132
Input port 3	211231	121232	203233

TABLE 3: Example Round 2 Score
	Output port 1	Output port 2	Output port 3
Input port 1	——	012012	111131
Input port 2	Winner	——	——
Input port 3	——	111132	202133

TABLE 4: Example Round 3 Score
	Output port 1	Output port 2	Output port 3
Input port 1	——	Winner	——
Input port 2	Winner	——	——
Input port 3	——	——	200133 (Winner)

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Phyworks demos 10G copper interconnects
Communications chip specialist Phyworks (Bristol, England) has demonstrated 10Gbits/s rack-to-rack copper interconnects of up to 30 metres using technology it originally developed for the optical module market. EE Times Europe's John Walko gets the story. Click here for details.

	Puzzled by a network processing design issue? Join former NPF CEO Colin Mick in discussing net processing design issues by clicking here!

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