Analog in a Digital Dementia
There are several approaches to integrating analog and digital functions on the same chip. However, the “special cell” treatment can simplify the task of incorporating all of the necessary functions on one piece of silicon.
By John Wright
Life for the digital designer is just now entering old age. Not only are the engineers who have made their careers out of innovative digital creations starting to
go through midlife crises, but the designs that once took on a purely 1 or 0 demeanor have started to show signs of aging as well. For the majority of today’s circuits, schematic capture is out of the question. Gate-level simulation times have increased to the point that without special equipment, simulation times are measured in weeks, not minutes. Functions that, in the past, found their place on the outskirts of system-on-chip (SOC) are now being integrated into the mainstream chip design.
There are many approaches to incorporating digital and analog functions onto the same chip. Two basic approaches stand out: treat the chip like a digital circuit and deal with the analog portion as a special cell, or treat the chip like an analog circuit and deal with the digital portion as a special cell. While both approaches have merit, the special-cell features help determine the approach one takes, and that approach can greatly simplify the task of incorporating all the necessary functions on one piece
of silicon.
Top-level functional simulation
Most digital designers have been using synthesis for years to create the digital functions they need. This approach lends itself to the top-down approach. “Top down” implies that functions are defined at various levels, allowing the designer to observe interactions between the functions. By focusing on the interactions between functions, the designer can quickly put together the desired features and uncover errors or problems.
Timing is seldom a concern at this stage of the design. Basic connectivity between functions and overall chip operation is key.
Often, other functions are incorporated onto the silicon from previous designs or other features on a board. These functions may be in the form of an FPGA or a gate-level netlist. Whatever form the functions or blocks are in, they need to be incorporated into the circuit, and the interactions between functions must be observed to ensure proper operation of the system.
Behavioral-level models (BLMs) may be created that emulate the functions of these parts. Care should be taken not to spend excessive time creating a BLM for the functions. The top-down method must accept BLMs, RTL code, or gate-level representations of these functions. Often, it is more accurate and less time consuming to simply include the netlist as a block while doing the top-level simulation, and an analog function may need to be included. These analog functions often take various forms including
phase-locked loops (PLLs), input comparators, digital-to-analog converters (DACs), analog-to-digital converters (ADCs), oscillators, and band-gap voltage references.
First-level analog behavioral level models
During top-down simulations, highly-accurate models of analog functions such as the ones listed previously are not required. Models that represent the basic functions of the analog cells provide enough accuracy to ensure proper operation. These basic analog models are referred to as
first-level models. An example of the output response for a first-level BLM for a band gap voltage reference is shown in
Figure 1a
, and the Spice-level simulation results are shown in
Figure 1b
.
Note that the first-level model does not vary over voltage and temperature. While this model would not be acceptable for multicorner simulations, it works well for top-level simulations, where continuity and basic
functionality are the focus.
Code Listing 1
shows the VerilogA representation for this model.
By using first-level models, valuable time is not wasted designing the analog block before the definition of the system is complete. This allows the designer the opportunity to quickly change analog functions and to observe changes in the system’s operation, without the costly overhead of cell design.
Analog function BLMs can be created by the designer, but they
are more often provided by the silicon vendor. The silicon vendor may have a library of first-level models to choose from, or they may generate the models as requested from Web-based model builders. If a designer decides to create behavioral-level models, care should be taken to create models that are realizable in silicon.
Silicon architects
Many companies employ silicon architects. Silicon architects are circuit designers who have a broad experience with many different types of
circuits and systems. They act as consultants to the designer during the verification phase and help the designer weigh trade-offs in circuit design. Silicon architects utilize Web-based model builders to handcraft models, including those features sought by the designer.
Silicon architects also provide a review of the analog functions that the designer wants to include on silicon, ensuring the feasibility of the embedded function. Highly-accurate analog functions can’t always be included on the same
chip with large amounts of digital logic, due to noise, power, or process constraints. The silicon architect can review the functions desired by the designer and make recommendations to help improve yield and feasibility.
Over-specifying an analog function results in additional cost in several ways. First, additional time is needed in the design of the analog function, increasing development costs. Specifying a complex function when a simpler function would suffice may result in silicon vendors
no-bidding or specifying unnecessary resources and span.
Second, in order to avoid noise issues, care must be taken whenever an analog function is included on a circuit with digital logic. Specifying an analog function that has strict noise tolerance may result in larger chip size and increased part price.
Third, over-specifying analog requirements results in increased test and validation time. This cost is generally passed on to the designer in the form of increased piece price. The final cost
is at board assembly where specifications will be checked after insertion. An additional cost is associated with the testing of tight tolerances. System architects often recommend other changes that help incorporate cost-saving ideas into the circuit’s design.
On occasion, designers feel uneasy about using BLMs for analog functions. Early digital designers had some of the same concerns regarding digital models for elements such as D flip-flops. Many analog designers refuse to use
behavioral-level models, saying that the accuracy of the model is not good enough to predict all the potential problems. The purpose of these top-level simulations is to verify functionality and connectivity, not to do system noise analysis.
Timing simulations
When functional simulations are complete, the designer can start the timing simulations. Because some designs will incorporate analog functions in the design, at some point in the circuit, analog and digital portions of the circuit will
interface with one another. These interface locations become critical to the operation of the circuit. Depending on the configuration of the circuit, different views of the analog and digital logic may be necessary.
Second-level behavioral models
While first-level behavioral models work well for functional simulations, a more accurate model is needed for timing simulations. Second-level models are often used in this situation. Second-level models are behavioral models that are derived from
a spice simulation’s output. These models are valid over voltage, temperature, and process fluctuations and allow the full-circuit simulation necessary for a higher degree of accuracy. The second-level model shown in
Figure 2
refers to the example of the band-gap voltage reference mentioned earlier.
Over supply voltage and temperature changes, the second-level behavioral model closely matches the spice simulations in
Figure 1b
. Second-level models should be able to match within 5% of the Spice simulations. These more accurate behavioral models allow digital designers to use the traditional corner simulations that they are accustomed to using, with a high degree of accuracy.
An example of the VerilogA representation of this second-level model is shown in
Code Listing 2
.
Generally, second-level models take less than a day to generate, upon completion of the
cell design.
Cell views
The mixed-signal simulator of choice must simulate digital circuits as well as transistor-level (or analog) circuits. When selecting a simulator, different views of each of the cells should be made available, so that as the design process progresses, the designer has the option of selecting either the behavioral view, gate-level view, or transistor-level view on a cell-by-cell basis.
Selecting several behavioral views for some parts of the circuit, while
other parts may be simulating at the transistor level is common. By not simulating all parts of the circuit at transistor levels, the simulation speed increases dramatically — as much as 100 times faster.
A logic simulator that is not vendor-specific should be selected. If the designer’s choice of vendors changes (because of capabilities or offering), it’s important to be able to continue to use the same simulation platform.
Layout aids
Once the analog cells have
been designed and verified, the cells are entered into layout. Here, the cells are laid out, or the geometric structure of the cells is created. This process is critical to the success of the design. Many layout techniques are used to ensure that the characteristics of the cells are maintained on silicon.
The matching of two transistors used in a comparator is an example of one of these characteristics. The two transistors would need to have as close to identical characteristics as possible in
order to eliminate variation in the comparator. One of the most common problems for the comparator is threshold mismatch. By utilizing certain layout techniques, threshold mismatch can be reduced, allowing for a more accurate comparison between input signals.
Most companies have incorporated automatic features that standardize certain layout configurations to avoid problems like threshold mismatch. These programs take the schematic representation of the cell and apply certain rule-based algorithms to
the layout, passing parameters to the layout such as transistor width and length, capacitance values, resistance values, and other critical parameters.
Once the transistor is realized, other menus allow for fine adjustments to the orientation and segmentation of the transistors, capacitors, and resistors. These aids save valuable time in avoiding rework and allowing the layout engineer to focus on the overall chip design instead of the cell layout.
Testing designs
The testing
of mixed-signal designs can be complex. Testing can be greatly simplified by using the simulations previously discussed. Many companies offer software that will convert the simulation outputs into a vector format suitable for tester usage. Full-circuit simulation enhances the probability that the circuit will be testable once it reaches manufacturing. Both the functions included on the circuit and the interactions between the circuit and the outside world must be monitored. Including these external
elements in the top-down simulation will greatly enhance the first-pass success.
Simulate for success
The ability to perform simulations with analog functions has been greatly augmented by the introduction of tools and methods that allow interaction between digital and analog functions:
- Top-level functional simulation can greatly improve the design flow and minimize rework.
- Behavioral-level models allow verification of connectivity between functions.
- Silicon architects provide expert advice for the inclusion of analog functions on the circuit.
- Cell views give the designer flexibility to examine different digital/ analog interfaces at different levels of complexity.
- Layout aids provide standard layout configurations for commonly used functions, reducing mismatch and noise.
Testing of the circuits is greatly simplified when complete simulations are provided to the test engi-neer. Capabilities are now available that
can greatly enhance the designer’s ability to provide analog functions on large digital designs and which will permit first-pass success.
John Wright is an engineering manager in mixed-signal methodologies for American Microsystems, Inc. John has a BSEEfrom Brigham Young University. He can be reached at
wright@poci.amis.com
.
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