Protecting High-Speed Communications Interfaces
The growing sophistication of today’s communication systems, coupled with highly-susceptible components, has rendered many of the more conventional methods of transient protection useless. Protecting sensitive components from the damaging effects of voltage transients is not
always a straightforward task.
By Bill Russell
Communication systems today increasingly rely on state-of-the-art, deep submicron, CMOS devices, featuring fabrication processes that utilize very fine line widths and thin dielectric layers. Unfortunately, transient voltages are unavoidable for most electronic devices. The smaller geometries of these electronics make them particularly sensitive to the effects of transient overvoltages. Moreover, adequate on-chip protection is, at best, a costly
proposition that may not even be possible. Therefore, external components designed to absorb or shunt high-energy surges away, are the primary line of defense for vulnerable electronic devices.
Protecting sensitive components from the damaging effects of voltage transients is not always a straightforward task. The growing sophistication of today’s communication systems, including faster operating frequencies and smaller designs, coupled with highly-susceptible components, has rendered many of
the more conventional methods of transient protection useless. Traditional solutions, such as spark gaps, zener diodes, RC networks, and clamping diodes can yield a false sense of security or, even worse, interfere with the expected operation of the circuit. For example, a “general” protection, 5-V transient voltage suppression (TVS) diode in a standard (DO-214AA) package can add several hundred pF of capacitance to a protected circuit, causing serious degradation of high-frequency signals.
High-speed interface protection, in particular, presents a unique challenge to the system designer — one that requires an innovative approach to protection technology and topology, as well as attention to industry standards for immunity requirements.
Transient threats
Transient voltages are randomly occurring “spikes” or pulses of voltage with an amplitude much higher than the normal operating voltage of the circuit. A typical transient event can last anywhere from tens of
nanoseconds to several milliseconds in duration. While transient voltages can be generated in a variety of ways, lightning and static discharge are the two most common threats to communications equipment.
Lightning transients are characterized by high-energy, long-duration pulses that last from tens to thousands of microseconds. A lightning-induced pulse is ordinarily defined by a double exponential waveform, indicated by an exponential rate of rise (from 10% to 90% of the peak) and an exponential decay
(to 50% of the peak). Common wave shapes are 10/1,000 µs (interpreted as 10 µs for rise time and 1,000 µs for decay) and 2/10 µs as defined by Bellcore specification 1089 for first-level (outer building) and second-level (intra-building) lightning pulses, respectively (
Figure 1
).
Electrostatic discharge (ESD) is another very common, potentially destructive, transient event. ESD occurs when accumulated static-electric charges are
discharged from one object to another object of lower potential. Static electricity is generated when two nonconductive materials are rubbed together, causing a transfer of electrons between the objects. Materials that exhibit ESD are referred to as the triboelectric series, and include nylon, paper, rubber, and vinyl.
The human body is an excellent accumulator of static charge. Consider the situation when a person, wearing shoes with insulating soles such as rubber, walks across a carpet (made of synthetic
material). As the carpet and shoes rub together, a charge is built up on the soles, which eventually transfers to the human body. When the person comes in contact with a conducting object such as a doorknob, a discharge occurs.
These discharge voltages can easily reach 15 kV. In fact, the most widely accepted ESD immunity standard, IEC 1000-4-2, uses the human body as the model to define ESD test voltages that range from 2 kV to 15 kV (air discharge). Peak currents are defined as high as 30A. The
discharge waveform reaches a peak in 1 ns with a total duration of 60 ns (
Figure 2
).
Static discharge is not exclusive to the human body, however. In fact, it is very common for network cables to become charged when handled. The static discharge occurs when the cable is then plugged into a connector on the PC board. This can cause a serious problem to Ethernet hardware, especially given the fact that a surprising number of manufacturers do not provide adequate
protection.
Protective elements
Protective elements must perform two basic functions: divert transient current away from the circuit, and clamp the transient voltage below the damage threshold of the protected ICs for a given pulse width. Furthermore, during normal circuit operation (no transient events), the protective element should not degrade the performance or function of the circuit it is protecting.
In general, suppression elements for high-speed interfaces require extremely fast
response times; low clamping and operating voltages; and, in the case of portable or handheld devices, they must occupy a minimum of board real estate. As a rule, the closer the transient suppression element is to the device it is protecting, the better its clamping characteristics must be.
Today, transient suppression strategies are based more and more on TVS diode technology, since it satisfies these requirements better and at a lower cost than other approaches. TVS diodes have a long, proven track record
for suppressing transient events at the PC-board level. Moreover, they are not susceptible to the degradation of their electrical characteristics, as long as they are operated within the device manufacturer’s published specifications.
Unfortunately, below 5V, conventional TVS diode technology becomes impractical. Conventional TVS diodes are silicon avalanche, p-n junction devices that are intentionally designed with a large junction area to enable them to handle high transient currents. This renders
them useless for most low-voltage applications, since capacitance is directly related to junction area, increasing exponentially as operating voltage decreases. The capacitive load presented by a conventional TVS diode to a signal in a high-speed or long-line application results in significant signal degradation or reflections. Additionally, the use of high concentrations of dopant impurities can yield devices that achieve very low stand-off voltages, but also results in a very high reverse leakage
current and higher-than-normal junction capacitance. An alternative approach to TVS diode technology is required.
The low-voltage, low-capacitance TVS approach that is commonly used today is the enhanced punch-through diode (EPD). This device design protects sensitive, low-voltage ICs in high-speed communication systems.
Generally, the topologies used for low-capacitance protection can be broken into three configurations. These approaches include low-capacitance shunt protection, rail-to-rail
protection, and low-capacitance bridge.
The low-capacitance shunt configuration takes advantage of the series-capacitance relationship. Because the net capacitance of two capacitors in series is less than the smallest component, TVS diodes can leverage this relationship by integrating a low-capacitance compensation rectifier in series with the TVS diode (
Figure 3
). Devices are available today that integrate one or more pairs of protection components, depending on
the application.
For example, a couple of applications that make common use of the low-capacitance shunt configuration are 10/100 and 10/100/1,000 Ethernet implementations. As Ethernet deployment makes the transition from relatively slow 10Base-T to Fast Ethernet and eventually Gigabit Ethernet, the controllers that must be employed become increasingly sensitive to latch-up or damage. This is because they must be fabricated in 0.35-µm or finer process technologies. This application is also an
appropriate example, because the potentially fatal discharge could originate from a charged cable or human body in a LAN application, or lightning-induced transients in a harsh telecommunications environment.
In a typical system, the twisted-pair interface for each Ethernet port consists of two differential signal pairs — one for the transmitter and one for the receiver, with the transmitter input being the most sensitive to damage. The fatal discharge occurs differentially across the transmit or receive
line pair, and is capacitively coupled through the transformer to the Ethernet controller chip.
The key to avoiding fatal discharge is to find a TVS diode that will clamp low enough to prevent latch-up or damage to the Ethernet IC, while minimizing the amount of added capacitance. The result is a device that provides a working voltage of 2.8 V, with a typical load capacitance of less than 5 pF.
In practice, protection in this application is achieved by connecting two such devices in an antiparallel
arrangement across each line pair. This ensures that the compensation diode is not reverse biased during transient conditions (
Figure 4
). During negative duration transients, the steering diode in the first device conducts in the forward direction, while the TVS will conduct in the reverse direction. During positive transients, the second device will conduct in the same manner. In this configuration, the total loading capacitance is the sum of the capacitance of
each device (typically less than 10 pF).
Another common means of protecting high-speed data lines is to employ low-capacitance steering diodes in a rail-to-rail configuration (
Figure 5
). Two devices per line are connected between two fixed voltage references, such as V
CC
and ground. When the transient voltage on the line exceeds the forward voltage (V
F
) drop of the diode plus the reference voltage, the diodes direct the surge to the
supply rail or ground. This method has several advantages, including low loading capacitance, fast response time, and the fact that it is inherently bidirectional (within the reference voltage range).
Serious problems may be encountered using this topology, however. First, discrete components are not usually rated to handle the high transient currents associated with ESD events (small signal rectifiers are typically constructed with very small junction areas). At high-current densities, the V
F
of these devices increases dramatically, until the power rating is exceeded. When this occurs, the protected component or even the protection diode may be damaged or destroyed.
Another problem with this configuration is the potential damage that may occur to downstream components as a result of redirecting the surge into the power supply rail. This can easily be overcome by adding a TVS diode to the power supply rail, in order to direct the surge to ground and clamp the voltage below the maximum rated
voltage of the device.
Careful consideration in layout is also important for an effective rail-to-rail topology. Parasitic inductance between the TVS diode and the steering diodes can cause a dramatic rise in clamping voltage. These problems are solved by using available integrated TVS/steering diode devices. These devices include surge-rated, low-capacitance steering diodes and a TVS diode in the same package. The integrated design reduces component count and minimizes parasitic inductance.
A third
low-capacitance protection topology is the bridge configuration shown in
Figure 6
. The bridge rectifiers reduce the effective loading capacitance, and route the incoming transient current safely through the TVS diode. Utilizing this topology, data lines can be protected in both common and differential modes.
Implementing this topology with discrete components is a bit tricky, however. For starters, selection of the proper bridge rectifiers is critical,
since the devices must be able to withstand high forward-surge currents with low V
F
characteristics. Also, proper care is required during device layout to reduce the effects of voltage overshoot from parasitic trace inductance.
A cleaner approach is the use of an integrated device, which combines a surge-rated diode bridge and a high-power TVS diode in a single SO-8 package. This device is specifically engineered for protecting high-speed telecommunications interfaces, and meets the transient
immunity requirements of Bellcore 1089 for intra-building interfaces. It can be used alone or in conjunction with integrated rail-to-rail devices for telecommunications interfaces, such as T1/E1, DS-3, and ISDN.
Board layout considerations
Board layout is critical in the suppression of extremely fast rise time ESD transients, since the voltage developed across an inductive load is proportional to the time-rate of current change through the load (V=Ldi/dt). The total clamping voltage seen by
the protected load will be the sum of the TVS clamping voltage, plus the voltage due to the parasitic inductance (V
C(TOT)
=V
C
+L di/dt). It is important to note that parasitic inductance in the protection path can result in significant voltage overshoot, reducing the effectiveness of the suppression circuit.
For example, an ESD-induced transient reaches its peak in approximately 1 ns. For a 30-A pulse (per IEC 1000-4-2, Level 4), 1 nH of series inductance increases the effective
clamping voltage by 30V (V=1x10-9 [30/1x10-9]). For maximum effectiveness, the following guidelines are recommended for board layout:
- Minimize the path length between the protection elements and the protected line
- Place protection elements as close to connectors as possible, to restrict transient coupling to nearby traces
- Minimize the path length (inductance) between connectors and protection elements.
Transient suppression products of the future will require even
higher levels of integration, lower capacitance, and smaller packages. Combining multiple technologies in the same package, while increasing performance characteristics, will provide the keys to future innovation. Industry trends, such as higher operating speeds, lower operating voltages, shrinking systems, and increased connectivity will drive these changes.
Bill Russell is an applications engineer at Semtech Corporation based in Newbury Park, CA. He received his BSEE from Southern Illinois
University at Carbondale in 1987. He can be reached at
Brussell@semtech.com.
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