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GREAT-Terry
Silicon photonics, I like this! Hope this "gradual changes" can be shorter so ...
patrick.mannion
Good summary of an important topic at DesignCon as we go to higher rates. We can ...
DesignCon panel: No magic bullet for crosstalk
Dylan McGrath
1/31/2012 2:15 AM EST
SANTA CLARA, Calif.—There is no perfect solution to the problem of crosstalk in modern communications ICs, an increasing concern as chip designers push devices into the realm of 28-gigabits per second and beyond, according to a panel of experts at DesignCon 2012 here Monday (Jan. 30).
Crosstalk—unintended interference of communication channels—can wreak havoc on a comms IC. But panelists, including representatives from test and measurement equipment vendors Tektronix Inc., Agilent Technologies Inc. and LeCroy Corp.—acknowledged that there are currently no tools that enable designers to adequately measure the effects of various types of crosstalk, thus preventing them from modifications that mitigate the problem.
To make matters worse, panelists said, there is a major disconnect between what communications standards such as PCI Express specify and what is actually needed to build chips that send and receive at cutting-edge speeds. "There is a fundamental difference between a silicon implementation and the reference equalizers you see in these emerging standards such as PCIExpress," said Mark Marlett, director of engineering responsible for serdes development at IP vendor Analog Bits Inc.
While there is no fail safe solution for measuring the effects of cross talk on a chip, Mike Peng Li, principal architect and distinguished engineer at programmable logic vendor Altera Corp., said the best existing solution is decision feedback equalizer (DFE), a type of circuit that can be inserted into a design to minimize crosstalk. "The DFE is the best medicine we have," Li said.
DFE is "a medicine that doesn't have the side effect of amplifying noise," said Martin Miller, chief scientist at LeCroy.
Panelists generally agreed with Li that DFE represents the best hope currently. But the method has its limitations. DFE has a problem with "avalanching" errors, said Ransom Stephens, a tech consultant and writer who served as the panel's moderator. "When it stumbles, it falls," Stephens said.
At one point , Stephens chided test and measurements on the panel, joking that they were working on solutions for the problem of crosstalk that they were reluctant to mention publicly. "There are proprietary solutions being developed," Stephens said after the panel concluded.
"We do have some ideas and some concepts on how to measure crosstalk and what we can do about it," said Pavel Zivny, a domain expert for serial data at Tektronix.
Panelists admitted that the ultimate solution to the crosstalk problem is a move to channels based on silicon photonics. Zivny joked at one point that audience members should drain their children's college funds to invest in any company involved in silicon photonics.
Li said the fundamental limit for comms chips using current CMOS technology is probably around 50- to 60-Gbps. After that, he said, some type of photonics scheme must be implemented for comms chips to push the envelope further. Li lamented the fact that only a very few companies, chiefly Intel Corp. and IBM Corp., are doing the fundamental research needed to move silicon photonics onto chips, but he predicted that "gradual changes" over the next three to four years would move that technology into semiconductors, much sooner than many observers think that it will happen.
For EE Times' full coverage of DesignCon, please visit here.
Crosstalk—unintended interference of communication channels—can wreak havoc on a comms IC. But panelists, including representatives from test and measurement equipment vendors Tektronix Inc., Agilent Technologies Inc. and LeCroy Corp.—acknowledged that there are currently no tools that enable designers to adequately measure the effects of various types of crosstalk, thus preventing them from modifications that mitigate the problem.
To make matters worse, panelists said, there is a major disconnect between what communications standards such as PCI Express specify and what is actually needed to build chips that send and receive at cutting-edge speeds. "There is a fundamental difference between a silicon implementation and the reference equalizers you see in these emerging standards such as PCIExpress," said Mark Marlett, director of engineering responsible for serdes development at IP vendor Analog Bits Inc.
While there is no fail safe solution for measuring the effects of cross talk on a chip, Mike Peng Li, principal architect and distinguished engineer at programmable logic vendor Altera Corp., said the best existing solution is decision feedback equalizer (DFE), a type of circuit that can be inserted into a design to minimize crosstalk. "The DFE is the best medicine we have," Li said.
DFE is "a medicine that doesn't have the side effect of amplifying noise," said Martin Miller, chief scientist at LeCroy.
Panelists generally agreed with Li that DFE represents the best hope currently. But the method has its limitations. DFE has a problem with "avalanching" errors, said Ransom Stephens, a tech consultant and writer who served as the panel's moderator. "When it stumbles, it falls," Stephens said.
At one point , Stephens chided test and measurements on the panel, joking that they were working on solutions for the problem of crosstalk that they were reluctant to mention publicly. "There are proprietary solutions being developed," Stephens said after the panel concluded.
"We do have some ideas and some concepts on how to measure crosstalk and what we can do about it," said Pavel Zivny, a domain expert for serial data at Tektronix.
Panelists admitted that the ultimate solution to the crosstalk problem is a move to channels based on silicon photonics. Zivny joked at one point that audience members should drain their children's college funds to invest in any company involved in silicon photonics.
Li said the fundamental limit for comms chips using current CMOS technology is probably around 50- to 60-Gbps. After that, he said, some type of photonics scheme must be implemented for comms chips to push the envelope further. Li lamented the fact that only a very few companies, chiefly Intel Corp. and IBM Corp., are doing the fundamental research needed to move silicon photonics onto chips, but he predicted that "gradual changes" over the next three to four years would move that technology into semiconductors, much sooner than many observers think that it will happen.
For EE Times' full coverage of DesignCon, please visit here.
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patrick.mannion
1/31/2012 9:08 AM EST
Good summary of an important topic at DesignCon as we go to higher rates. We can fiddle with various combinations of linear equalizers (FIR, CTLE) and DFEs to reconstitute a signal, but as the data rates go up, the power and cost of clock and data recovery to up also, to a point that jumping to photonic paths becomes a necessity. Of course, we hope that while we're pushing the limits of linear equalizers and DFEs to their max, that the cost of silicon photonics comes down -- way down -- in the meantime. Great topic! Thanks Dylan.
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GREAT-Terry
1/31/2012 10:34 PM EST
Silicon photonics, I like this! Hope this "gradual changes" can be shorter so faster chips with higher computation power can be developed.
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