With the amount of storage increasing in mobile phones, there is a clear trend to shift away from traditional NOR-based flash memory architectures toward NAND-based devices. However, as pointed out in Part 1 of this article, NAND technology has some inherent limitations such as bit-flipping, the existence of bad blocks, a limited lifespan, non-standard interface, the requirement for software management, and the fact that it is not possible to boot from NAND. All these issues must be dealt with to insure reliability both of stored data and the handset itself.
Fortunately, some new NAND design options enhance the benefits and overcome some of the limitations in existing NAND devices. In Part 2 of this series, we'll examine the architecture options available to solve traditional NAND limitations and look at the tradeoffs of each of these approaches.
Option 1: Raw NAND (GPIOs and Software)
Unlike NOR, NAND does not have the standard electrical interface found in most of today's chipsets. Although highly not recommended, it is feasible to connect NAND to a chipset without a specialized NAND bus by configuring spare chipset GPIO pins (assuming such signals are available) to emulate a NAND bus.
In such a case, the task of managing NAND properly falls solely on the software. Such software would need to implement error detection and correction (EDC/ECC) algorithms, as well as an efficient flash translation layer to provide bad block management, wear-leveling, dynamic mapping and to perform other managerial tasks.
Such an implementation has a high overhead in terms of the GPIO usage and software. More critical, it drastically reduces performance, due mostly to the heavy error detection code that must be executed every time data is read or written to/from the flash.
Another significant drawback is that such an implementation does not enable the system to boot from the NAND device. This means that the system must be designed with a separate boot device.
Option 2: NAND with External Controller
NAND can be used in conjunction with a specialized companion controller. Such a controller can serve as a bridge between the NAND device and the chipset, as shown in Figure 3. The NAND will then reside (through the controller) on the same bus as a NOR device would.
Figure 3: Diagram of a NAND flash with external controller.
In addition to handling the electrical interface, a companion controller may include implementation of an error detection algorithm to reduce the software overhead. It may also include the error correction mechanism, but since error correction is required less frequently, implementing it by software is more efficient.
However, this is a relatively costly approach since a second chip is required, increasing both the bill of materials (BOM) cost and the printed circuit board (PCB) size. The NAND controller may require from 6 x 6 to 10 x 10 mm of precious PCB space, in addition to the space occupied by the NAND media.
Another disadvantage of this solution is that it lacks a system approach. When using a specialized NAND controller it is not clear, for example, which component will supply the software to manage the NAND and whether or not it will be optimized for the specialized controller. Other questions that may arise are: will the software be procured from the NAND manufacturer who presumably is very familiar with the media and best suited to optimize the software for it? Or will it be procured from the controller vendor, who has the deep understanding of the controller required to optimize the software for the specific logic?
There are also open questions on the support side: If there is a bug in software or hardware, will the flash vendor, the controller vendor or the host platform vendor resolve it?
It is clear that such a solution fails to provide the developer with a clear point of contact for integration support and maintenance, leaving this responsibility on the designer's shoulders.
Option 3: NAND with Chipset Controller
Thanks to the growing market requirement for NAND flash solutions over the past year, a number of mobile application processor vendors have attempted to provide out-of-the-box NAND support by embedding a NAND controller inside their processors. This activity is best represented by Texas Instruments' newest members of their OMAP family and by Qualcomm's new members of their MSM family of products.
The application processor vendors provide an additional NAND bus to overcome the hardware interface issue that was one of the factors preventing NAND adoption in the past (Figure 4).
Figure 4: NAND with controller embedded in a wireless application processor.
While this approach is clearly an improvement over previous alternatives, it addresses only part of the problem. Also, it lacks the flexibility to support different flash devices. During the lengthy design and market cycles that such a new application processor requires, NAND flash will inevitably have evolved, and a corresponding evolution in NAND attributes will have occurred. Therefore, the chipset will invariably support outdated flash devices instead of the current product on the market to coincide with application processor availability.
The market already shows evidence of this time gap. The following recent major developments in NAND flash are not all supported by application processors:
- 16-bit devices — Most current application processors have added NAND support for 8-bit devices, the popular interface at the time of the processor design. Today, 16-bit flash devices are available from both Toshiba and Samsung. The inability to connect these new 16-bit devices to the application processor means that there is a large gap between the performance they can support and the higher performance that 16-bit NAND devices can provide.
- Page sizes — The page size used in NAND flash has changed over the past year. This is an important factor when reading/writing to the flash. With proper design, the new page size can be used to increase performance.
- Multi-Level Cell (MLC) NAND technology — A new revolution in the NAND flash world that doubles the capacity of a given NAND die, MLC NAND technology is a very attractive solution to reduce the silicon size and cost.
The fact that NAND flash improvements such as these cannot be used in wireless chipsets with embedded NAND controllers greatly reduces the attractiveness of such a solution.
Here, too, as with the previous implementation using NAND and an external controller, it is not clear who will develop the required software and provide the ongoing maintenance and support. This remains to be seen, since such application processors have just begun to enter the market.
Booting from NAND remains a major weakness, since none of the chipset implementations includes error correction for the boot code stored in NAND. This can result in fatal errors and even a system crash.
Option 4: NAND Using the Standard Memory Bus
The ideal solution for high-capacity memory that designers can easily integrated into mobile handsets, without a proprietary interface, is a NAND-based flash storage device that combines the best characteristics of NOR and NAND.
Such a NAND-based device serves as a memory system by providing a range of system capabilities far beyond data storage. It uses a NOR-like hardware interface to enable the device to be easily connected to any platform. It stores code to boot the OS, thereby offering designers the option of eliminating a separate boot device from the system to save both board real estate and reduce BOM costs. An automatic download mechanism resides in the controller to allow system boot in a fast and reliable fashion.
It delivers the high level of data reliability required for boot operations, achieves high write performance, and is characterized by high density so that more data and code can be stored in less silicon, achieving a smaller die size and thereby reducing costs.
To realize all of these benefits in a NAND-based device, flash management software is critical. In addition to handling reliability issues, it allows easy device management under any operating system. The combination of NAND and the right flash management software can maximize performance and ease-of-use by balancing the effort of managing the NAND flash between hardware and software. For example, heavy error detection algorithms can be implemented in hardware, while the lighter and less frequently used error correction algorithms can be implemented in software.
Figure 5 shows such a system architecture with DiskOnChip. The main difference between this implementation and those shown in Figure 3 and Figure 4 is that DiskOnChip resides on the memory bus and does not require a new, specialized bus solely for NAND.
Figure 5: Diagram of the DiskOnChip architecture.
DiskOnChip is available in two versions, as a monolithic device or as a multi-chip packaging (MCP) device. The monolithic version implements the controller on the same silicon die as the flash array to maximize performance, reliability, and cost structure. The MCP product packs together the controller and NAND flash on a single die, and optionally other memory devices, each on separate silicon dies, to maximize design flexibility. Traditionally, MCP devices are more popular in the embedded market while the monolithic version is found more widely in the PDA and handset market.
Option 5: High-Density MLC NAND
NAND-based devices that use MLC NAND instead of binary technology [also known as single-level cell (SLC) technology] achieve even smaller die sizes by storing 2 bits per cell instead of the traditional 1 bit per cell. In fact, MLC NAND doubles the capacity per given silicon size, as shown in Figure 6.
Figure 6: Compared with binary NAND, MLC NAND doubles flash density.
While MLC NAND represents a breakthrough in cost structure, the limitations of the technology are making it hard and tedious to integrate into real-life applications. The major limitations are substantially slower performance and problematic reliability. Performance limitations are being overcome by advanced technology that implements parallel multi-plane operations and provides support for direct memory access (DMA) and burst mode. Reliability is being enhanced with advanced EDC/ECC mechanisms.
Wrap Up
Clearly, the need for higher densities in mobiles provides a new opportunity for designers to turn to NAND flash memory. But, to be successful, designers must overcome the limitations that NAND flash provides. Fortunately, as Part 2 demonstrated, designers now have many architectural choices to overcome these limitations.
Editor's Note: To view Part 1 of this article, click here.
About the Authors
Arie Tal is a technical support director at M-Systems. Mr. Tal is responsible for recognizing emerging market trends and defining the next generations of DiskOnChip and TrueFFS software features. Arie received a BA in economics from The Technion, and MBA from Haifa University, and an Electronic Engineering degree from Netanya College. He and can be reached at arie.tal@m-sys.com.
Ziv Paz is product manager at M-Systems. Ziv received a B.Sc. with honors in Computer and Electrical Engineering from Ben Gurion University, Israel in 1994. He can be reached at ziv.paz@m-sys.com.
