Link bandwidth can be a slippery animal. Without careful thought on the front end of the design, attenuation, reflections and system noise can quickly turn a planned 10 Gbits/s link into one with a much less throughput. With a thoughtful approach to the entire signal path and inclusion of well-chosen equalization techniques coupled with extensive simulation, much of the bandwidth can be regained before it has a chance to disappear.
For any discussion of bandwidth of a single channel, it is important to understand what the maximum channel capacity limit is given the number of signaling levels and the amount of noise in the system. For this we go to the Shannon-Hartley Theorem, which gives the designer a way to determine the amount of information that can be transferred based on signal to noise ratios. The baud rate is defined as twice the base band frequency and corresponds to the number of voltage state changes per second. This is often referred to as the element rate. A single element can define multiple bits depending on the number of voltage levels used in the signaling. The information rate is the element rate multiplied by the base 2 log of the number of levels used for signaling. This can be transformed into base 10 for simpler calculation.
I = 2 * F * Log2 M
Or
I = 2 * F * 3.32 * Log10 M
As shown in Figure 1, 2 voltage levels will yield 1 bit of information per baud, 4 levels will yield 2 bits per baud, 8 levels will yield 3 bits, etc.
Figure 1: Bits of information for 2 and 4 level signaling.
Noise in the system will degrade the channel capacity by making the different voltage levels less distinguishable potentially causing bit errors. In a noisy environment, The Shannon Limit governs the information rate by relating the information rate to the RMS signal to noise ratio and the baseband frequency, irrespective of the number of signaling levels.
I = F * 3.32 * Log10 1 + (S/N)
In a four level system operating at 100 MHz, the ideal channel capacity is:
2 X (100 MHz) X (3.32 x Log10 4 ) = 400 Mbps.
In order to maintain this rate, Shannon-Hartley determines the minimum signal to noise ratio required.
(400 Mbps/ (100 MHz X 3.32)) = Log10 1+ S/N
16.02 "1 = S/N = 15.02.
While this implies that the tradeoffs between operating frequency and signal to noise ratio can be made, these may not be practical. An increase in the signal to noise ratio point to a lower operating frequency, however this would require an increase in the number of available voltage levels from four to eight in to transfer more information at a lower frequency.
Sources of Eye Closure
Eye closure is a common way to evaluate the impact of signal to noise ratio on a link's bandwidth. In a single graphical representation an eye pattern captures the impact of losses on the net itself as well as the influence of outside aggressor signals. There are four primary mechanisms that lead to received eye closure:
- Signal Attenuation
- Reflections
- Intra-pair Differential Skew
- Crosstalk and Common Mode Impedance Noise
Signal Attenuation
A signal is attenuated by primarily conductive losses, which vary with the square root of frequency, and dielectric losses, which vary directly with frequency. As shown in the attenuation curve in Figure 2, the dielectric losses dominate above approximately 1 GHz.
Figure 2: Conductive losses dominate below 1 GHz.
Board losses alone can result in significant eye closure, irrespective of reflections and crosstalk. To a degree this can be managed with careful board/cable design and material selection. When these methods have been exhausted, equalization techniques can be used to regain the integrity of the eye. These techniques are myriad, with passive and active solutions available. They can be applied to either the transmit or receive end of the link.
Conductive losses can be controlled by overall width and, of course, length of the trace. Copper weight does not impact the AC losses because skin effect causes the current to flow only on the surface of the trace as shown in Figure 3a. Stripline routing can reduce losses for single ended signal, by allowing current to flow on the top and bottom surfaces of the conductor as in Figure 3b. The advantage is less pronounced with the routing of differential signals since a well-balanced pair will have no net current flowing in the reference plane (Figure 3c). In reality a perfectly balanced pair is unlikely. Consequently, some common mode current will flow in the return plane even with differential pairs. Therefore, the stripline configuration may offer a small advantage.
Figure 3: Current flow in stripline and microstrip configurations.
Dielectric losses are related to the loss tangents of the core and build up materials used to manufacture PC boards. FR-4 has a loss tangent on the order of .02, whereas lower loss boards, available for a price premium, are available with values below .004. Besides having more expensive raw materials, these are often more difficult to process, increasing application cost. Many applications use the more robust FR-4 constructions on the component cards, while reserving the more expensive low loss materials for the longer backplane runs.
Microstrip constructions are lower loss than equivalent stripline constructions because they include air in the effective dielectric cross section. Because of this, microstrips see regular use in high data rate applications. Additional care must be taken to manage any EMI and mode dispersion issues that may result from using these constructions.
Equalization
Losses attenuate the higher frequencies more than the lower frequencies. This causes the information contained on the high bit rate edges of the signal to be lost along the channel. Equalization restores this information by boosting the high frequency and/or attenuating the low frequency content. The result is an output eye with less jitter and consequently more information.
Long cable applications often use passive equalization to suppress the low frequency content of the signal. This can be done using a simple RC circuit shown in Figure 4.
Figure 4: Equalizer frequency response.
When the circuit highlighted in Figure 4 is put in series with the trace, the response of the interconnect is more equal over the frequency spectrum. Figure 5 illustrates the impact of a 4.5 dB equalizer in the frequency domain as well as the improved jitter performance of a 30 inch trace simulated at 10 Gbits/s. This solution works over a relatively narrow range of cable lengths and can be prone to impedance mismatch. One solution to this is to build the equalization into the raw cable as done with W.L. Gore's Eye-Opener PLUS family of cables. With these types of cables, a thin conductive region is plated over a non-conductive core forcing all of the current to flow in the "skin" of the conductor at low frequencies. This suppresses the low frequency content of the signals.
Figure 5: Impact of a 4.5 dB equalizer in the frequency domain.
Active transmit equalization comes in the form of pre-emphasis and de-emphasis. As shown in Figure 6, pre-emphasis increases the voltage level if more than one bit time is spent at a DC level. This increases the high frequency content of the signal. The drawback is that the increased voltage on the signal edge can lead to increased crosstalk within the system. De-emphasis keeps the high frequency content constant while decreasing the amplitude of the low frequency data when the signal remains at a given DC level for more than one bit time. The amount of pre-emphasis or de-emphasis depends on the number of "taps" in the circuitry. These taps monitor the previous current and future bits to determine the level of emphasis to place on the current bit being launched.
Figure 6: Diagram illustrating pre-emphasis and de-emphasis.
Adaptive receive equalizers are designed to monitor the incoming data and shape an inverse transfer function to the data that restores the high frequency components as necessary. Whereas transmitter resident techniques respond only to the launched bitstream, adaptive equalization can also respond to losses and reflections in the received signal as well as variations in the drive PVT. These solutions are often more complex to implement, requiring silicon for high-resolution sampling in digital implementations and wide bandwidth receivers operating at the maximum bit rate in analog implementations.
On to Part 2
In Part 2 of this article, we'll look at the impact of reflections on overalllink bandwidth. to view Part 2, click here.
About the Author
John Ellis is co-founder and vice president of signal integrity at TriCN. He hols a BS in electrical engineering from Lehigh University and can be reached at jellis@tricn.com.
