Sunnyvale, Calif., — The HyperTransport Consortium has released version 1.05 of its I/O Link Specification and initiated a compatibility program to promote the use of the chip-to-chip interconnection specification.
The latest release of the spec defines several important new HyperTransport technology features, including an updated switch function, enhanced PCI-X 2.0 interworking support, increased concurrency and 64-bit addressing.
"This new backward compatible specification paves the way for the HyperTransport industry to extend the capabilities of the technology without making existing products obsolete," said Gabriele Sartori, President of the HyperTransport Technology Consortium.
The HyperTransport switch function enables the connection of virtually unlimited numbers of HyperTransport devices. And by switching traffic locally the switch reduces latency and potential bandwidth logjams.
The switch definition supports the concatenation of multiple width buses that in turn allows system designers to apply just the right amount of bandwidth in a particular section of a design. This in turn reduces overall system cost while maintaining maximum chip-to-chip I/O bandwidth.
Release 1.05 enhanced PCI-X 2.0 interworking features simplify the connection of HyperTransport-enabled systems to PCI-X 2.0 subsystems. Included are support for PCI-X 2.0 error indications and the ability to handle device configuration messages of up to 4K bytes. This supports the 128 byte burst message feature in PCI-X 2.0.
The new concurrency feature allows a system to have up to 128 requests outstanding rather than the 32 requests in the existing spec, eliminating the potential bottleneck in networking applications. This can occur in networking or server applications where a given data stream pipeline is "clogged" with outstanding requests that have not been fulfilled.
Finally, Release 1.05 64-bit addressing feature extends the original specification's 40-bit address in order to support large address spaces needed by some large networking and server applications. The 64-bit command feature is backward compatible with older address schemes, making the 64-bit address optional and enabled on a link-by-link basis.
Brian Holden, Principal Engineer in PMC-Sierra's MIPS Processor Division and Chair of the Technical Working Group, said: "Over the past year we worked with our member companies to understand exactly what was needed to extend the existing specification to speed the development of networking and server applications. This new specification gives system designers added features that will be helpful in large HyperTransport-based server applications."
Compatibility Program
The consortium's latest effort to spread the use of HyperTransport technology focuses on a set of electrical and protocol checklists and a Device Under Test Connector definition that HyperTransport-enabled product manufacturers can use to help ensure compatibility between their devices.
"This new program is an essential step for the HyperTransport industry," said Sartori. "It gives users and designers a means of comparing HyperTransport-enabled devices with the ultimate aim of ensuring that products from one manufacturer will easily integrate with others. By precisely defining a list of interoperability tests that check that a given implementation meets the stringent requirements of the HyperTransport specification, the checklists give manufacturers a valuable set of tools to help them produce interoperable parts."
Todd Hironaka, Chair of the HyperTransport Infrastructure and Senior Hardware Engineer, Technology Center at Cisco Systems commented: "This is an important first step to ensure system designers can reliably apply HyperTransport technology regardless of the product source."
The consortium plans over this year to develop further technical specifications, specifically to aid the security of users.
