If you're aiming at the low-cost emerging market, phone-on-a-chip is your short-term solution. If not, think about it for the long term.

By Cedric Paillard, TECHInsights
Courtesy of Mobile Handset DesignLine Aug 17, 2006

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It's generally accepted that any RF sub-system will eventually be integrated with the digital baseband processor on the same chip (i.e., CMOS process) to save space, cost, and power consumption. Because the RF section is typically much smaller in area than the digital section, the migration to smaller process nodes is likely to be a requirement for new RF devices in the future.

The principal challenge in deep submicron design is the low supply voltage that impacts every RF component (mixers, VCOs, frequency dividers, variable-gain stages, power amplifiers, and, in some cases, LNAs). The next challenges to address are the transistors' falling output impedance, nonlinearity, gate leakage current (and its associated noise), and problems of stress-induced mismatches. On the other hand, CMOS tends to provide transistors with higher transistor cut-off frequencies and a larger number of metal levels (better inductors) to help CMOS RF IC designers reduce power dissipation and/or area.

From a market perspective, the need to deliver lower cost RF ICs has driven the need for more integration. Wireless transceiver integration has made dramatic progress in the last decade. GSM phones—single-band, voice-only—started with a component count around 400, employing half a dozen or more chips in different technologies for signal processing alone.

Today we see two-chip and even single-chip implementations for wireless LAN or Bluetooth on the market. Cellular phones today routinely cover three or four bands and support not only voice but also higher data rates. Cameras, MP3 players, e-mail, etc., are added to the basic phone functionality. Whereas two-chip solutions and biCMOS technologies for the RF front end are still standard for cellular phones, the first plain CMOS transceivers are available on the market and even single-chip CMOS solutions are being sampled. Many numbers have been discussed in about the potential advantages of such approaches (75% reduction in components, 65% reduction in board area, 50% reduction in manufacturing costs, less than $20 BOM, and so on) to ensure that the need of the "emerging markets" will be met.

There is no doubt that the next challenges will be the low-cost phone for emerging countries on one side, and multi-band, multi-standard terminals on the other. Quad-band GSM/EDGE together with UMTS, CDMA for phone functionality, FM radio, digital radio, digital TV for entertainment, Bluetooth and WLAN for connectivity, GPS for localization, navigation and location-based services, and, finally, megapixel camera, MP3 functionality, and games will all be available in a future high-end phone. For the low-cost phone, three or four major players addressing this market with a "phone-on-a-chip." Infineon, with the E-GOLDradio (PMB7870), TI's LoCosto device, and Silicon Labs with the Aerofone device (Si4905) are the three main ones currently shipping product to lead customers.

These three solutions represent state-of-the art architectures and design of wireless transceivers. The first two integrate a proven stand-alone transceiver into a single-chip phone; the second is pursuing digitally-oriented concepts.

Both the Infineon and SiLabs solutions are devices derived from previous generations. The E-GOLDradio RF architecture is derived from the single RF CMOS transceiver (SMARTiSD) and the Aerofone comes directly from SiLabs Aero family. Both devices are implemented in 130-nm CMOS supporting similar functionality. Does this mean that for low cost cellular handset SoC low risk is an advantage? Absolutely. At 130-nm CMOS, both companies benefit from a well-established process and architecture and are probably cheaper than 90-nm, even if the die could have been smaller with smaller geometries. Both the SMARTiSD and Aero architectures have been stable for a long time and have yielded positively in production. On the manufacturing side of the phone, this approach provides limited changes in performance and software and could actually reduce lowest production cost, easiest board integration, and the highest flexibility in system optimization.

TI's approach has been to re-use their newly developed Digital Radio Processor (DRP) architecture in 90-nm CMOS. Most analysts consider this decision to be part of a long-term approach by TI to the cellular RF IC market. TI decided to bite the bullet today, forecasting the need to migrate whatever architecture they might come up with below 90-nm CMOS. As a result, TI elected to release their device slightly after their competition, but expect to compensate for this later with a more scalable architecture. The future will tell who was right. No one will disagree with long-term approach and it's not difficult to imagine 65-nm CMOS being required in a few years for this kind of application. Basically, today, 90-nm CMOS with a conventional architecture might be a bit more risky than a traditional implementation.

What's the big deal about a phone-on-a-chip? If all the key components have been implemented before in the same technology, integration issues become the major problems. Both Infineon and SiLabs and to a lesser extent TI, must cope with crosstalk from digital into analog and RF blocks. The fastest digital clock speed on the digital side is around 100 MHz, while the fastest clock speed on the RF would be around 25% of that clock.

For GSM/EDGE applications, the preference is to use a multiple of 26 MHz that can be derived from 52 or 104 MHz. Crosstalk is not a small matter in these conditions and not only for those specific clocks frequency, but also with regards to their higher harmonics.

To counteract this issue, the overall system architecture plays an important role. In the case of the E-GOLDradio, a zero-IF approach is used in the receive path to help block and reduce sensitivity to spurs in the LO signal. The transmit path uses a direct modulation (with a sigma-delta PLL) and pseudo-digitally controlled oscillator that can be adjusted in frequency and therefore resist possible coupling between high-frequency harmonics and the VCO. The implementation of a digitally controlled oscillator is a recent trend providing flexibility and programmability for such issues.

Agile calibration and programmability of the RF transceiver integrated with large CMOS blocks should be considered a must. This is a way of enabling reliable complete system, integration with high performance and high yield, while minimizing external components. This implies a good system analysis ahead of time, but the benefits are multiple. Calibration and programmability provides accurate frequency response and gain for each block while potentially increasing dynamic range when required. In addition to minimizing coupling, VCO phase noise, and leakage, calibration, and programmability could reduce dc offsets and improve matching of IQ path and differential signals. With such techniques operating in the normal transmit and receive switching time, all blocks can be calibrated for bandwidth, center frequency, and gain.

The E-GOLDradio is one example, but other implementations provide additional guidance to solve integration issues. A highly linear transceiver combined with distributed filtering/amplification stages offers good performance while integrated near high-speed digital. A well-defined frequency planning also minimizes the effects of synchronous digital noise.

From an implementation point of view, single-chip integration suffers from coupling through CMOS substrate and package/board implementation (this is where an early view at the overall system can be rewarding). Both coupling effect can be managed. Large spacing between RF and digital blocks with plenty of substrate contact will go a long way toward reduce coupling through CMOS substrate. Isolating noisy pins, lots of on-chip de-coupling, buffering wherever possible, and isolating board routing should take care of coupling through package and board.

Note that all three solutions address the same market (GSM/EDGE) and not CDMA2000 or UMTS (see the table). There are a few reasons for this. First, GSM/EDGE has a significant market share in emerging markets. Second, to benchmark CDMA and GSM systems, some key elements need to be compared. Peak-to-average ratio (PAR) and bandwidth are often good indicators of a design's complexity. The higher the PAR, the more complex the transmitter will be. The wider the bandwidth, the more complex the receiver will be.

About the author
Cedric Paillard is the vice-president of TECHinsights at Semiconductor Insights. He holds BS and MS degrees in VLSI System Engineering from the University of Manchester Institute of Science and Technology. He also has a Bachelor of Engineering from the Ecole Superieure de Technolgie Electrique. Paillard can be reached at cedricp@semiconductor.com.