SAN MATEO, Calif. — Rambus Inc. is developing a set of physical-layer chips for the upcoming PCI Express interconnect and has won a licensing agreement for them from PC chip set maker ALi Corp. of Taiwan.
The company currently has an Express PHY core available in a 130-nanometer process of Taiwan Semiconductor Manufacturing Co. Ltd. aimed at memory controllers, graphics chips and switches. It is developing for sampling by year's end a low-cost PHY geared for I/O controllers made in a 180-nm process of United Microelectronics Corp.
The parts were derived from a Rambus physical-layer chip for the Xaui Ethernet interface. The company has a 90-nm Xaui part now in development at TSMC, which it will use as a basis for its next-generation Express PHY.
With Intel stepping on the gas to put the fast serial Express interconnect in a broad range of desktops, notebooks and servers next year, Rambus spotted an opportunity to leverage its core design and consulting expertise, said Jean-Marc Patenaude, marketing director of the logic interface division at Rambus (Los Altos, Calif.).
"The average PCI design is still at 66 MHz, and now they are being asked to move to 2.5 Gbits/second, so I just smell danger," he said.
PLX Technology said in February that it would license Express technology from Rambus for its switch chips. Now Rambus is pursuing PC chip set and graphics designers like Silicon Integrated Systems, Nvidia and ATI Technologies, who must move to Express in the next six months to stay current with Intel.
Intel Corp., the world's largest maker of PC chip sets, is expected to design its own Express PHY chips. Rambus will compete with Express cores from Artisan, Tality and other IP makers as well as in-house designs.
The PCI Special Interest Group that oversees the Express spec is set to vote on a 1.0a version soon and will hold its first Express interoperability workshop Dec. 18. The latest version of the spec made changes in chapter four, which defines the physical layer. While errata are still coming in on the Express spec, sources close to the work said PCI Express is still roughly on schedule.
Separately, Rambus is considering a variant of its Redwood parallel interconnect. The new version, which could ship late next year, would support LVDS interconnects like HyperTransport and SPI 4.2 and use the 6.25-Gbit/s Redwood technology as an optional turbo mode.
The variant, targeting network processors, is now in test silicon. But Rambus has not decided on a final feature set or delivery date.
