NEW ORLEANS — With a few surprises in its choices of embedded cores, Motorola Inc.'s Semiconductor Products Sector will unveil architectural details of its third-generation PowerQuicc communication-processor architecture this week. The introduction will take place at the Smart Networks Developers Forum here, though sampling is not anticipated until early next year.
Some cores of the MPC8560 PowerQuicc III, such as the PowerPC e500 RISC executive core and the Ocean crossbar switch fabric, were part of a PowerQuicc road map provided by Motorola executives last summer. But others are unexpected. Moreover, the use of an embedded RapidIO interconnect underscores Motorola's commitment to that technology. Other interface options, such as PCI-X, double-data-rate SDRAM and dual Gigabit Ethernet ports, are less controversial.
This is the first generation of PowerQuicc to utilize system-on-chip design methodology, which Motorola says it may share with key accounts in order to offer optimized versions of PowerQuicc III. In general, however, SoC design was used for internal core and bus placement, not necessarily for ease of customization. Certain cores, such as the e500 RISC and the coherency module, remain full-custom blocks, but SoC design is used for interconnecting primary modules with the buses and glue logic.
A stripped-down version of PowerQuicc III, the MPC8540, was described at last year's Microprocessor Forum, but product-marketing manager Mike Shoemake said that the 8540 represents a limited-function device, without serial communications controllers or multichannel HDLC support. The 8560 will be the primary PowerQuicc III processor, with the 8540 serving subsidiary roles in systems such as enterprise routers or 3G basestations.
1-GHz RISC core
The newer e500 core in PowerQuicc III supports speeds up to 1 GHz, against 600 MHz in the 603e core used in PowerQuicc II. The new RISC core has a seven-stage pipeline and a 256-kbyte Level 2 cache. The eight-way set-associative cache can be segmented into 128 kbytes each of standard cache and private SRAM, or dedicated fully for cache or private SRAM.
The communications processor module is used in several generations of PowerQuicc, serving channel-aggregation duties for a mix of protocols, such as ATM, HDLC, Ethernet and TDM. But where the speed of the module topped out at 700 Mbits/second in PowerQuicc II, it has been redesigned to support up to 1 Gbit/s. The module also has its own memory subsystem, split into blocks of instruction RAM, instruction ROM and dual-port RAM. This allows it to support larger microcode packages and to be upgraded for new protocol support in the field.
The real performance edge comes from the combination of coherency module and Ocean switch fabric. The coherency module offloads the processor bus, making sure that traffic goes to the processor only if coherency checking is required. In association with this, an internal switch fabric based on RapidIO handles transaction queuing and flow control inside the device. The fabric, used solely for internal chip communications, offers 22 Gbits/s of internal bandwidth for protocol bridging.
RapidIO also is brought out externally through a parallel 8-bit port. If an 8560 is used in parallel, or in conjunction with an 8540, they will be connected via the parallel RapidIO port. Chief PowerQuicc architect Stefan Singer said that Motorola is looking at a variety of future alternatives linked via the internal Ocean fabric, such as serial RapidIO or HyperTransport.
"We can consider any interconnect, but RapidIO for us still provides superior features for the type of architecture PowerQuicc III represents," Singer said. "If we really see the need to add a different type of interface quickly, we also could look at the development of bridge chips with our partners." Motorola works with such vendors as Tundra Semiconductor Corp. and PLX Technology Inc. on bridging devices.
The 8560 currently is going through what Singer called "billions of verification cycles," a critical step in advanced processor design. The company remains confident that fully functioning prototypes will be ready by the end of the calendar year, he said.
