As Table 1 points out, the biggest benefit that GaAs amplifiers provide is higher carrier mobility, which results in a higher f_t and f_max as compared to Si, and also allows for the use of larger device geometries having higher breakdown voltages, for any specific frequency. This in turn allows higher bias voltages to be used, with correspondingly lower currents, for any given output power. This reduced current, in turn, results in reduced source and drain parasitic capacitances, which limit high operational frequencies and are particularly problematic for switch-mode amplifiers.

The transconductance, g_m, for GaAs is also much larger than that attainable with Si CMOS. This larger transconductance provides more gain per stage in an amplifier, resulting in fewer stages being required for any specific gain requirement leading to reduced die area and lower overall system cost.

The input impedance of a Si CMOS device is highly reactive with very high input impedance. The input impedance of a GaAs pHEMT device, on the other hand, is much easier to match into. This ease of matching reduces any residual mismatch power loss, and decreases the die area required by the passive matching circuits, again reducing overall cost.

GaAs processes incorporate lower resistance metal layers (Au) than are used in Si CMOS (Al and Cu). As a result, the spiral inductors and MIM capacitors used in the passive matching circuits provide higher Qs and lower loss. The semi-insulating substrate of GaAs also contributes to higher Qs and lower loss for the inductors and MIM capacitors, as compared to Si.

Finally, the semi-insulating substrate also reduces the source and drain parasitic capacitances of the transistors. This reduction enables GaAs devices to achieve greater efficiency than Si CMOS devices at a given frequency.

As a result of the above advantages, it is clear that GaAs possesses many strong advantages for microwave power amplifiers. In addition to stand-alone, linear amplifiers, GaAs presents strong advantages for switch-mode power amplifiers. Further, with appropriate LINC-based computational engines in a companion CMOS (or BiCMOS) transceiver chip, these switch-mode power amplifiers become very attractive for advanced modulation schemes used by high data rate applications.

Analyzing Switched-Mode Power Amps
Designers looking to implement GaAs power amplifiers in their WLAN designs will encounter six classes of devices: Class A, Class B, Class A/B, Class D, Class E, and Class F. Table 2 provides a comparison of the significant features for these various class of amplifiers.

As Table 2 shows, the switch-mode Class D, Class E, and Class F amplifiers attain higher efficiencies in WLAN designs than their linear Class A, Class B or Class A/B counterparts, but with very low or time varying output impedances. In each case, the high efficiency is achieved by limiting (or not allowing) current flow through the active devices when a voltage drop exists across their output terminals, and by limiting (or not allowing) any voltage to exist across their output terminals when current is flowing through the devices.

Let's take a closer look at the Class D, E, and F amplifiers. We'll start with Class D devices. A transformer-coupled, voltage-switching configuration of a Class D amplifier is shown in Figure 1, and its voltage and current waveforms are shown in Figure 2.

In Figures 1 and 2, the input signals, v_in and its complement cause the two transistors to switch on and off alternately. During the half-cycle when the bottom transistor is on, its drain voltage is zero. This places a voltage of V_cc across the bottom half of the primary winding of the transformer, which is transformed by the turns-ratio to (n/m) V_cc on the secondary winding. This also causes the voltage presented to the drain of the top transistor to be +2 V_cc.

During the half-cycle when the top transistor is on, V_cc is applied across the top half of the primary causing -(n/m) V_cc to appear on the secondary, and +2 V_cc to be present at the drain of the bottom transistor.

The secondary voltage is then a square wave, and its fundamental passes through the output resonator to create a sinusoidal output current. This sinusoidal output current is supported on the input winding by two half sinusoids flowing alternatively in the bottom half and top half of the input winding (and hence alternatively through the top transistor and the bottom transistor). Since the current flows in each device when the drain voltage is zero, and since no current flows when the drain voltage is +2 V_cc , no power is absorbed by the devices and the theoretical efficiency is 100 percent.

Although it possesses a theoretical efficiency of 100 percent, Class D amplifiers are limited in practice due to their drain (or collector) parasitic capacitances. These parasitics prevent the voltage waveforms from switching on and off instantaneously, resulting in a voltage being applied across the transistors output while current is flowing through the transistors.

A similar effect results if the load contains a significant reactance component. Here the drain voltage waveforms remain square wave, but the output current is shifted in phase. This will result in a negative current flowing in each device when turning on, which in turn will charge the parasitic capacitances and create a voltage spike.

The difficulties associated with parasitic capacitances in Class D amplifiers are addressed by the Class E architecture. Let's take a closer look.

Class E Amps
A single-ended Class E amplifier is shown in Figure 3, and its voltage and current waveforms are presented in Figure 4.

Here a series tuned L_oC₀ circuit connects the drain to the load, and a shunt capacitance C connects to ground. The shunt capacitance consists of the transistor's parasitic capacitance and a capacitance that is added to cause the transistor to ideally pass no current when there is a voltage across the drain. This desirable condition is achieved by allowing the drain voltage to continuously vary, rather than being limited to a square-wave as is the case for a Class D amplifier. It should be noted that a significant overshoot in drain voltage occurs as a result, and this overshoot must be kept below the breakdown voltage of the device.

For optimal performance, not only must the drain voltage be zero when the device turns on (and starts to conduct current), the slope of drain voltage should also be zero when the device turns on. This ensures that the current flowing from the shunt capacitance is zero, and hence the drain current is ensured to be zero just as the transistor turns on. Since both the drain-source voltage and the drain current are zero at the transition, power dissipation in the device is negligible.

Although it possesses a theoretical efficiency of 100 percent, the Class E amplifier is limited in practice due to the high Q requirement needed to suppress harmonics, which in turn allows the drain voltage to reach zero volts with a zero slope with time. As for Class D amplifiers, changes in load reactance can also produce negative drain voltages and/or drain currents during parts of the RF cycle.

The Class F architecture avoids these difficulties, as well as those provided by the Class D.

Class F Amplification
A single-ended Class F amplifier is shown in Figure 5 and its voltage and current waveforms are presented in Figure 6.

A Class F amplifier has a load network that has resonances at one or more harmonics, as well as at the fundamental. In Figure 5, the transistor acts as a current source, producing a half sine wave. The fundamental frequency tuned-circuit at the output shunts all harmonics to ground, producing a sinusoidal output voltage. The third-harmonic resonator, however, provides a high impedance (at the third harmonic) to allow the voltage on the drain of the device to maintain a third harmonic component. The correct amplitude and phase of the third harmonic with respect to the fundamental will flatten the drain voltage, resulting in higher efficiency.

Class F Performance
Simulations of a half-micron, GaAs MESFET operating in Class F at 5-GHz were taken using Agilent's Advanced Design System EDA tool (Figure 7). Here the drain is biased at 5 V and the gate at 12 V.

As can be seen, when the input gate drive voltage, Vgate, is increased from a peak value of 1.8 V to a value of 2.7 V. Thus, Vdrain becomes an increasingly square wave. This is due to the amplitude and phase of the third harmonic component moving towards the correct values needed for Class F operation. Upon passing through the resonator portions of the Class F amplifier, this square wave drain voltage is converted into the sinusoidal output voltage, Vout.

The simulated efficiency and output power of the Class F amplifier is also given in the table as the amplifier moves into Class F operation. The simulated efficiency of 86.9% is in good agreement with the predicted theoretical value of 88.4% for Class F operation.

Power Amp Linearization Techniques
As with linear power amplifiers, switch-mode power amplifiers used in LINC based architectures may require linearization in order to provide high performance for advanced modulation schemes such as OFDM. The linearization compensates for AM-to-AM distortion (compression) as well as AM-to-PM distortion to provide a clean output signal with very little out-of-band emissions, and in-band EVM (Error Vector Magnitude). The principal linearization techniques available are discussed below.

Several classical techniques are available to overcome linearity difficulties in a transmitter, such as feedback, feedforward, and predistortion. Each technique has its own attractive features and limitations, as discussed below. The correct choice for a linearization technique for a power amplifier will depend on the relative ease in dealing with the different limitations.

Feedback techniques are not easy to incorporate in RF power amplifiers. For a highly non-linear power amplifier, a high loop gain must be realized to provide the linearization required. Loop instabilities, arising from various resonances of parasitic couplings, package parasitics, and transient currents, make feedback power amplifiers subject to spontaneous oscillation.

Feedback techniques can, however, be applied successfully to a combined up-converter/power amplifier. Here, the problem of high loop gain is alleviated by allocating most of the loop gain to the lower IF frequency, where resonances are not so prevalent.

Figure 8 shows a scenario where loop gain is allocated to the lower IF frequency. In this figure, a portion of the output power is downconverted to the original IF frequency. In effect, the loop attempts to make the modulation of V_RF a replica of the modulation of V_IF.

To ensure stability, the closed-loop phase must not approach 180 degrees for any frequency having a loop gain greater than 1. To achieve this, the phase, θ of the reference frequency (LO) used to down-convert the RF, can be set to ensure a safe margin. A significant problem is the dependence of θ on temperature, processing parameters, and output power, making it difficult to guarantee stability.

Feedback techniques for transmitters incorporating independent upconversion of quadrature signals, to be applied to a common power amplifier, have been attempted. Here quadrature downconversion in the feedback loop converts the RF back into two quadrature IF components, ready for comparison with the two original quadrature IF signals. Due to the added complexity, and sensitivity to temperature and process, this architecture is not commonly used.

The Feedforward Approach
The output voltage waveform from a non-linear power amplifier can be considered as the summation of an amplified replica of the input signal, and an error signal. The feedforward architecture determines this error, and subtracts it from the amplified output waveform (Figure 9).

In Figure 9, a factor equal to the gain of the power amplifier attenuates a portion of the power amplifier's output signal. This attenuated output signal is compared with the original input signal to create an error signal. Finally, this error signal is amplified by the same gain as the power amplifier, and subtracted from its output signal.

At high frequencies, such as 5-GHz, the two amplifiers in the feedforward architecture exhibit substantial phase shifts. This must be compensated for with the use of the two, true-time delay elements, as shown in Figure 9.

Unlike feedback architectures, feedforward techniques are inherently stable, even with substantial phase shifts in each component. However, the passive true-time delay elements are lossy, and the degree of linearization achieved is dependent on the gain and phase (true-time delay) matching of the signals applied to each subtractor.

As an example, for a gain mismatch of five percent and a phase mismatch of five degrees, the suppression of the power in the intermodulation products will be limited to just 20 dB. Finally, in order to not compromise the overall output power, the output subtractor must have low power loss.

Predistortion Methods
Predistortion architectures attempt to provide the inverse input/output (I/O) function of the saturating power amplifier. In effect, the predistortion circuit provides enhanced gain for large amplitude signals, before they are applied to the power amplifier. Further, the predistortion circuit attempts to compensate for any amplitude-dependent insertion-phase, by providing the opposite phase change.

Predistortion circuits can operate at the RF frequency of the power amplifier, or they can operate at an IF or baseband frequency before upconversion, as shown in Figure 10. When predistortion is applied before upconversion, it can be realized as either an analog or digital implementation.

Since predistortion does not incorporate any closed feedback loops, it does not exhibit any stability problems. However, achieving an accurate inverse input-output function of that of the power amplifier requires significant system level as well as digital and RF IC design expertise.

Wrap Up
A stand-alone GaAs power amplifier has many significant advantages when compared with an integrated CMOS (or Bi-CMOS) equivalent. The availability of computational engines in a companion transceiver chip can enable the use of classes of power amplifiers, such as switch-mode architectures, that are not normally considered for advanced modulation schemes. Further, linearization techniques may be incorporated for the power amplifier, again using the computational engines available in the companion transceiver chip.

Although all three classes of switch-mode amplifiers possess very high theoretical efficiencies, Class D is limited in practice due to its drain (collector) parasitics, and Class E by its high Q requirement and its sensitivity to load variations. Class F may provide promising performance including very high efficiency when used in the appropriate transmitter architecture, and realized in an appropriate process.

Linearization of power amplifiers for radios using advanced modulation schemes having large peak-to-average ratios, is important in achieving high efficiency, and hence low power consumption. The three common linearization techniques: feedback; feedforward; and predistortion have unique operational requirements as well as limitations.